Spring 2004 CSCI 311 / ENGR 212 / ECE 212 E-Homework Assignments

Due to the difficulties of completing the Electronic Assignment with breadboards for remote students, I have decided that students can complete the assignments in one of three ways:

1. By making a breadboard
2. By specifying and testing a circuit using the MultiMedia Logic Simulator
3. By specifying and testing a circuit in VHDL using the Symphony EDA simuluation package

The only rule is that you use either MultiMedia Logic or Symphony EDA for all three assignments. The due date for all electronic homework is the day of the Final Exam.

MultiMedia Logic simulator

The MultiMedia Logic simulator is a product of Softronics, Inc. A windows version of the simulator can be downloaded from Softronics' Welcome to MultiMedia Logic page. There is a tutorial for MultiMedia Logic that is available under it's Help pull-down menu. Read it before you start designing a circuit.

I little more information about MultMedia Logic is available from Lab 2 (combinational logic), Lab 3 (MUXes), Lab 4 (sequential logic) of an old UNCA CSCI 255 offering.

VHDL simulation

The suggested VHDL simulation tool is VHDL Simili program of Symphony EDA. If you don't already have a copy of VHDL Simili, you can download a free version for either Windows or Linux from the VHDL Simili 2.3 download site.

At UNCA, Simili 2.3 is installed on the Linux workstations in Robinson 004. There the simulator is called sonata.

There are numerous VHDL tutorials available on the Internet. I've listed a couple below, but you can google for many more.

• VHDL Simili User's Manual
• Jan Van der Spiegel, University of Pennsylvania Department of Electrical Engineering
• Green Mountain Computing Systems, Inc

VHDL Examples

These are all examples of a "majority" circuit. These majority circuits examine three bits and return the most popular bits. The combinational examples examine three concurrent input bits. The sequential examples examine three sequential bits.

• Combination
  • Behavioral implementation -- one line of "code"
  • Structural implementation -- uses four NAND gates
• Sequential
  • Procedural implementation -- looks like a CS1 program
  • Procedural implementation -- uses explicit states
  • Procedural implementation -- mimics descrete flip-flops
• ZIP file with all examples and associated test bench drivers

E-Homework assignments

1. Constructing Test, Input/Output, and Combinational Circuits
   • MultiMedia Logic starter file -- MultiMedia format
   • MultiMedia Logic starter file -- ZIP format
   • VHDL starter file
   • VHDL testbench file
   • VHDL stater files -- ZIP format
   • Symphony EDA "scope" capture
2. 2-Bit Ripple-Carry Adder / Combinational Design with MUXes
   • MultiMedia Logic starter file -- MultiMedia format
   • MultiMedia Logic starter file -- ZIP format
   • VHDL starter file -- circuit 1
   • VHDL starter file -- circuit 2
   • VHDL testbench file
   • VHDL stater files -- ZIP format
   • Symphony EDA "scope" capture
3. Transition Counter
   • MultiMedia Logic starter file -- MultiMedia format
   • MultiMedia Logic starter file -- ZIP format
   • VHDL starter file
   • VHDL testbench file
   • VHDL stater files -- ZIP format
   • Symphony EDA "scope" capture

Possibly useful reference material

• Old CSCI 255 lab similar with E-homework 1 -- contains pictures of breadboard