-- Outline for a VHDL implementation for NCSU ECE 212 E-Homework 2 first stage
--   (c) J. Dean Brock, 2004
--   EXCEPT that the LS153 is based on an example from
--      John Wakerly, Digital Design: Principles and Practices

-- This one should use a Multiplexor

-- An invertor for our structural description
library ieee ;
use ieee.std_logic_1164.all ;
entity INV is
  port (I: in std_logic; O: out std_logic);
end INV;
architecture INV_arch_jdb of INV is
begin
  O <= not I ;
end INV_arch_jdb ;

-- The LS153 function is based on the ABEL Z74X153 module of
--      John Wakerly, Digital Design: Principles and Practices
library ieee ;
use ieee.std_logic_1164.all ;
entity LS153 is
    port ( 
      A, B                : in STD_LOGIC ;     -- Selector inputs
      G1_L, G2_L          : in STD_LOGIC ;     -- Enables
      C10, C11, C12, C13  : in STD_LOGIC ;     -- Data input set 1
      C20, C21, C22, C23  : in STD_LOGIC ;     -- Data input set 2
      Y1, Y2              : out STD_LOGIC      -- Data outputs (both)
    ) ;
end LS153;
architecture LS153_arch_jdb of LS153 is
begin
  Y1 <= not G1_L and
          ((not B and not A and C10)
           or (not B and A and C11)
           or (B and not A and C12)
           or (B and A and C13)) ;
  Y2 <= not G2_L and
          ((not B and not A and C20)
           or (not B and A and C21)
           or (B and not A and C22)
           or (B and A and C23)) ;
end LS153_arch_jdb ;


-- Finally the actual circuit
library ieee ;
use ieee.std_logic_1164.all ;
entity HMWK2C2 is
  port (
    X    : in  STD_LOGIC;
    Y    : in  STD_LOGIC;
    Cin  : in  STD_LOGIC;
    S    : out STD_LOGIC;
    Cout : out STD_LOGIC
  ) ;
end HMWK2C2 ;

architecture HMWK2C2_arch_jdb of HMWK2C2 is
  signal CinNot : STD_LOGIC ;
  -- Again, in the style of John Wakerly's Z74X153 ABEL module
  component LS153
    port ( 
      A    : in STD_LOGIC ;
      B    : in STD_LOGIC ;
      G1_L : in STD_LOGIC ;
      G2_L : in STD_LOGIC ;
      C10  : in STD_LOGIC ;
      C11  : in STD_LOGIC ;
      C12  : in STD_LOGIC ;
      C13  : in STD_LOGIC ;
      C20  : in STD_LOGIC ;
      C21  : in STD_LOGIC ;
      C22  : in STD_LOGIC ;
      C23  : in STD_LOGIC ;
      Y1   : out STD_LOGIC ;
      Y2   : out STD_LOGIC
    ) ;
  end component ;

  -- nothing but an invertor
  component INV
    port (
      I    : in STD_LOGIC ;
      O    : out STD_LOGIC
    ) ;
  end component ; 

begin  -- HMWK2C2_arch_jdb

  -- YOUR STRUCTURAL SPECIFICATION GOES HERE

end HMWK2C2_arch_jdb;