-- A combinational implementation of the vote-3 circuit using a behavioral description
--   (c) J. Dean Brock, 2004

library ieee ;
use ieee.std_logic_1164.all ;

entity VOTE3CB is
  port (
    X  : in  STD_LOGIC;
    Y  : in  STD_LOGIC;
    Z  : in  STD_LOGIC;
    M  : out STD_LOGIC
  ) ;
end VOTE3CB ;

architecture VOTE3CB_arch_JDB of VOTE3CB is
begin  -- VOTE3CB_arch_JDB

  M <= (X and Y) or (X and Z) or (Y and Z);

end VOTE3CB_arch_JDB;