-- Outline for a VHDL implementation for NCSU ECE 212 E-Homework 2 first stage
--   (c) J. Dean Brock, 2004

-- This one should be "random" logic

library ieee ;
use ieee.std_logic_1164.all ;

entity HMWK2C1 is
  port (
    X    : in  STD_LOGIC;
    Y    : in  STD_LOGIC;
    Cin  : in  STD_LOGIC;
    S    : out STD_LOGIC;
    Cout : out STD_LOGIC
  ) ;
end HMWK2C1 ;

architecture HMWK2C1_arch_XXX of HMWK2C1 is
begin  -- HMWK2C1_arch_XXX

  -- YOUR BEHAVIORAL SPECIFICATION GOES HERE

end HMWK2C1_arch_XXX;