-- Outline of a VHDL implementation for NCSU ECE 212 E-Homework 3
--   (c) J. Dean Brock, 2004
library ieee ;
use ieee.std_logic_1164.all ;

entity HMWK3 is
  port (
        Reset:  in  STD_LOGIC;
        Clock:  in  STD_LOGIC;
        SerIn:  in  STD_LOGIC;
        SerOut: out STD_LOGIC
  ); 
end HMWK3 ;

architecture HMWK3_arch_jdb of HMWK3 is
  -- ADD NEEDED SIGNAL DEFINITIONS HERE

begin  -- HMWK3_arch_jdb

  -- YOUR PROCEDURAL SPECIFICATION GOES HERE
  process(Clock, Reset)
    -- ADD NEEDED VARIABLE DECLARATIONS HERE
  begin
    if Reset = '1' then
      -- ADD RESET INITIALIZATION HERE
    elsif Clock'event and Clock = '1' then
      -- ADD STATE TRANSITION AND OUTPUT HERE
    end if ;
  end process ;

end HMWK3_arch_jdb;