-- A sequential implementation of the vote-3 circuit using a
-- procedural description to implement a state table.
--   (c) J. Dean Brock, 2004

library ieee ;
use ieee.std_logic_1164.all ;

entity VOTE3SPS is
  port (
        Reset:  in  STD_LOGIC;
        Clock:  in  STD_LOGIC;
        SerIn:  in  STD_LOGIC;
        SerOut: out STD_LOGIC
  );
end VOTE3SPS ;

architecture VOTE3SPS_arch_JDB of VOTE3SPS is
  type state_type is (SAout0, SAout1, SB0, SB1, SC0, SC1, SC2) ;
  signal MYSTATE : state_type := SAout0 ;
begin  -- VOTE3SPS_arch_JDB

  -- Next state logic
  process(Clock, Reset)
  begin
    if Reset = '1' then
      MYSTATE <= SAout0 ;
    elsif Clock'event and Clock = '1' then
      case MYSTATE is
        -- Let's start at the very beginning
        when SAout0 | SAout1 =>
          if SerIn = '0' then
            MYSTATE <= SB0 ;
          else
            MYSTATE <= SB1 ;
          end if ;
        -- Read 0
        when SB0 =>
          if SerIn = '0' then
            MYSTATE <= SC0 ;
          else
            MYSTATE <= SC1 ;
          end if ;
        -- Read 1
        when SB1 =>
          if SerIn = '0' then
            MYSTATE <= SC1 ;
          else
            MYSTATE <= SC2 ;
          end if ;
        -- Read 00
        when SC0 =>
          MYSTATE <= SAout0 ;
        -- Read 01 or 10
        when SC1 =>
          if SerIn = '0' then
            MYSTATE <= SAout0 ;
          else
            MYSTATE <= SAout1 ;
          end if ;
        when SC2 =>
          MYSTATE <= SAout1 ;
      end case ;
    end if ;
  end process ;
  
  -- output logic
  process(MYSTATE)
  begin
    case MYSTATE is
      when SAout1 =>
        SerOut <= '1' ;
      when SAout0 | SB0 | SB1 | SC0 | SC1 | SC2 =>
        SerOut <= '0' ;
    end case ;
  end process ;

end VOTE3SPS_arch_JDB;