-- Testbench circuit for NCSU ECE 212 E-Homework 1
--    (c) J. Dean Brock, 2004
--    EXCEPT for CONV_STD_LOGIC function taken from
--      John Wakerly, Digital Design: Principles and Practices
library ieee ;
use ieee.std_logic_1164.all ;

entity HMWK2_tb is
    generic (whocares : boolean := true) ;
end HMWK2_tb ;
  
architecture TESTBENCH of HMWK2_tb IS
  component HMWK2C1 IS
    port (
    X    : in  STD_LOGIC;
    Y    : in  STD_LOGIC;
    Cin  : in  STD_LOGIC;
    S    : out STD_LOGIC;
    Cout : out STD_LOGIC
  ) ;
  end component ;

  component HMWK2C2 IS
    port (
    X    : in  STD_LOGIC;
    Y    : in  STD_LOGIC;
    Cin  : in  STD_LOGIC;
    S    : out STD_LOGIC;
    Cout : out STD_LOGIC
  ) ;
  end component ;

  constant period : time := 200 ns ;

  signal TestX     : STD_LOGIC_VECTOR (2 downto 1) ;
  signal TestY     : STD_LOGIC_VECTOR (2 downto 1) ;
  signal TestCin   : STD_LOGIC;
  signal TestS     : STD_LOGIC_VECTOR (2 downto 1) ;
  signal TestCout  : STD_LOGIC ;
  signal CStage1   : STD_LOGIC ;

  -- The CONV_STD_LOGIC function is taken from
  --      John Wakerly, Digital Design: Principles and Practices
  function CONV_STD_LOGIC_VECTOR(ARG: integer; SIZE: integer)
                     return STD_LOGIC_VECTOR is
    variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0) ;
    variable temp: integer ;
  begin
    temp := ARG ;
    for i in 0 to SIZE-1 loop
      if (temp mod 2) = 1 then
        result(i) := '1' ;
      else
        result(i) := '0' ;
      end if ;
      temp := temp / 2 ;
    end loop ;
    return result ;
  end ; 

begin  -- TESTBENCH

  TestMod1: HMWK2C1
    port map (
      Cin  => TestCin ,
      X    => TestX(1) ,
      Y    => TestY(1) ,
      Cout => Cstage1,
      S    => TestS(1) ) ;

  TestMod2: HMWK2C2
    port map (
      Cin  => Cstage1 ,
      X    => TestX(2) ,
      Y    => TestY(2) ,
      Cout => TestCout,
      S    => TestS(2) ) ;

   TestLoop: process
   begin
     TestCin <= '0' ;
     while (true) loop
       for i in 0 to 3 loop
         TestX <= CONV_STD_LOGIC_VECTOR(i, 2) ;
         for j in 0 to 3 loop
           TestY <= CONV_STD_LOGIC_VECTOR(j, 2) ;
             wait for period ;
         end loop ;
       end loop ;
       TestCin <= not TestCin ;
     end loop ;
   end process ;

end TESTBENCH;