-- Testbench circuit for NCSU ECE 212 E-Homework 3
--    (c) J. Dean Brock, 2004
library ieee ;
use ieee.std_logic_1164.all ;

entity HMWK3_tb is
    generic (whocares : boolean := true) ;
end HMWK3_tb ;
  
architecture TESTBENCH of HMWK3_tb is
  component HMWK3 is
    port (
        Reset:  in  STD_LOGIC;
        Clock:  in  STD_LOGIC;
        SerIn:  in  STD_LOGIC;
        SerOut: out STD_LOGIC
    );
  end component ; 

  constant period : time := 200 ns ;
  
  signal TestReset  : STD_LOGIC ;
  signal TestClock  : STD_LOGIC ;
  signal TestSerIn  : STD_LOGIC ;
  signal TestSerOut : STD_LOGIC ;
  
begin -- TESTBENCH
  TestMod: HMWK3
    port map (
      Reset  => TestReset ,
      Clock  => TestClock ,
      SerIn  => TestSerIn ,
      SerOut => TestSerOut
    ) ;
    
    
  TestDrive: process
  begin
    TestReset <= '0' ;
    while true loop
      for i in 0 to 10 loop
        for j in 0 to 3 loop
          wait for period/2 ;
          TestClock <= '0' ;
          wait for period/4 ;
          TestSerIn <= '0' ;
          wait for period/4 ;
          TestClock <= '1' ;
        end loop ;
        for j in 0 to 3 loop
          wait for period/2 ;
          TestClock <= '0' ;
          wait for period/4 ;
          TestSerIn <= '1' ;
          wait for period/4 ;
          TestClock <= '1' ;
        end loop ;
      end loop ;
      wait for period/4 ;
      TestReset <= '1' ;
      wait for period/4 ;
      TestClock <= '0' ;
      wait for period/4 ;
      TestSerIn <= '0' ;
      wait for period/4 ;
      TestClock <= '1' ;
      wait for period/4 ;
      TestReset <= '0' ;
      wait for period/4 ;
      TestClock <= '0' ;
      wait for period/4 ;
      TestSerIn <= '0' ;
      wait for period/4 ;
      TestClock <= '1' ;
      for i in 0 to 7 loop
        for j in 0 to 5 loop
          wait for period/2 ;
          TestClock <= '0' ;
          wait for period/4 ;
          TestSerIn <= '0' ;
          wait for period/4 ;
          TestClock <= '1' ;
        end loop ;
        for j in 0 to 3 loop
          wait for period/2 ;
          TestClock <= '0' ;
          wait for period/4 ;
          TestSerIn <= '1' ;
          wait for period/4 ;
          TestClock <= '1' ;
        end loop ;
      end loop ;
      wait for period/4 ;
      TestReset <= '1' ;
      wait for period/4 ;
      TestClock <= '0' ;
      wait for period/4 ;
      TestSerIn <= '0' ;
      wait for period/4 ;
      TestClock <= '1' ;
      wait for period/4 ;
      TestReset <= '0' ;
      wait for period/4 ;
      TestClock <= '0' ;
      wait for period/4 ;
      TestSerIn <= '0' ;
      wait for period/4 ;
      TestClock <= '1' ;
    end loop ;
  end process ;
  
end TESTBENCH ;