-- A combinational implementation of the vote-3 circuit
--   using a structural description with NAND gates
--   (c) J. Dean Brock, 2004

-- A two-input NAND
library ieee ;
use ieee.std_logic_1164.all ;
entity NAND2 is
    port (
      A, B    : in STD_LOGIC ;  -- The two inputs
      N       : out STD_LOGIC   -- The output
    ) ; 
end NAND2;
architecture NAND2_arch_JDB of NAND2 is
begin
  N <= not (A and B) ;
end NAND2_arch_JDB ;

-- A three-input NAND
library ieee ;
use ieee.std_logic_1164.all ;
entity NAND3 is
    port (
      A, B, C : in STD_LOGIC ;  -- The three inputs
      N       : out STD_LOGIC   -- The output
    ) ; 
end NAND3;
architecture NAND3_arch_JDB of NAND3 is
begin
  N <= not (A and B and C) ;
end NAND3_arch_JDB ;


-- Finally the structural definition
library ieee ;
use ieee.std_logic_1164.all ;

entity VOTE3CS is
  port (
    X  : in  STD_LOGIC;
    Y  : in  STD_LOGIC;
    Z  : in  STD_LOGIC;
    M  : out STD_LOGIC
  ) ;
end VOTE3CS ;

architecture VOTE3CS_arch_JDB of VOTE3CS is
  -- The wires to connect the components
  signal TermXY : STD_LOGIC ;
  signal TermXZ : STD_LOGIC ;
  signal TermYZ : STD_LOGIC ;
  -- The components
  component NAND2
      port (
      A, B    : in STD_LOGIC ;  -- The two inputs
      N       : out STD_LOGIC   -- The output
    ) ; 
  end component;
  component NAND3
      port (
      A, B, C : in STD_LOGIC ;  -- The three inputs
      N       : out STD_LOGIC   -- The output
    ) ; 
  end component;

begin  -- VOTE3CS_arch_JDB
  -- The NANDs of the AND plane
  N0: NAND2 port map(A => X, B => Y, N => TermXY) ;
  N1: NAND2 port map(A => X, B => Z, N => TermXZ) ;
  N2: NAND2 port map(A => Y, B => Z, N => TermYZ) ;
  -- The NAND of the OR plane
  N3: NAND3 port map(A => TermXY, B => TermXZ, C => TermYZ, N => M) ;
end VOTE3CS_arch_JDB;