-- A sequential implementation of the vote-3 circuit using Flip-Flops
-- This is a hard way to solve the problem, but it illustrates a point
--   (c) J. Dean Brock, 2004

-- Here's the original state table
-- 
--           input                     STATE
--          0     1    out           ASSIGNMENT
-- SAo0    SB0   SB1    0               000
-- SAo1    SB0   SB1    1               001
-- SB0     SC0   SC1    0               010
-- SB1     SC1   SC2    0               011
-- SC0     SAo0  SAoO   0               100
-- SC1     SAo0  SAo1   0               101
-- SC2     SAo1  SAo1   0               110
--
-- Assuming three flip-flops Q0, Q1, Q2, input Sin, and output Sout, espresso gives
--
-- Q0* = Q0' Q1
-- Q1* = Q1 Q2 Sin + Q0' Q1'
-- Q2* = Q0' Q2' Sin + Q1 Q2 Sin' + Q1' Q2 Sin + Q0 Q1
-- Sout = Q0' Q1' Q2

library ieee ;
use ieee.std_logic_1164.all ;

entity VOTE3SFF is
  port (
        Reset:  in  STD_LOGIC;
        Clock:  in  STD_LOGIC;
        SerIn:  in  STD_LOGIC;
        SerOut: out STD_LOGIC
  );
end VOTE3SFF ;

architecture VOTE3SFF_arch_JDB of VOTE3SFF is
  -- The state variables
  signal Q0, Q1, Q2 : bit ;
begin  -- VOTE3SFF_arch_JDB

  -- Next state logic
  process(Clock, Reset)
  begin
    if Reset = '1' then
      Q0 <= '0' ;
      Q1 <= '0' ;
      Q2 <= '0' ;
    elsif Clock'event and Clock = '1' then
      Q0 <= not Q0 and Q1 ;
      Q1 <= (Q1 and Q2 and to_bit(SerIn)) or (not Q0 and not Q1) ;
      Q2 <= (not Q0 and not Q2 and to_bit(SerIn)) or (Q1 and Q2 and not to_bit(SerIn))
                or (not Q1 and Q2 and to_bit(SerIn)) or (Q0 and Q1) ;
    end if ;
  end process ;

  -- Output function  
  SerOut <= To_StdULogic(not Q0 and not Q1 and Q2) ;

end VOTE3SFF_arch_JDB;