-- Outline for a VHDL implementation for NCSU ECE 212 E-Homework 1
--   (c) J. Dean Brock, 2004

library ieee ;
use ieee.std_logic_1164.all ;

entity HMWK1 is
  port (
    A2  : in  STD_LOGIC;
    A1  : in  STD_LOGIC;
    A0  : in  STD_LOGIC;
    F2  : out STD_LOGIC;
    F1  : out STD_LOGIC;
    F0  : out STD_LOGIC
  ) ;
end HMWK1 ;

architecture HMWK1_arch_XXX of HMWK1 is
begin  -- HMWK1_arch_XXX

  -- YOUR BEHAVIORAL SPECIFICATION GOES HERE

end HMWK1_arch_XXX ;