Each assignment has a specified due time and submission mechanism. Late assignments will be accepted with a penalty of 1% per hour.
| # | Due | Description | Weight | |
|---|---|---|---|---|
| 1 | In class, 26 January | voltage and time | 20 | 😇 |
| 2 | In class, 2 February | working backwards | 20 | 😇 |
| 3 | 5:10 PM, 12 February | SystemVerilog for FSM | 40 | 😇 |
| 4 | 5:10 PM, 1 March | SystemVerilog testbench | 40 | |
| 5A | 5:10 PM, 22 March | SystemVerilog ALU – Part A | 5 | |
| 5B | 11:55 PM, 29 March | SystemVerilog ALU – Part B | 10 | |
| 5C | 11:55 PM, 5 April | SystemVerilog ALU – Part C | 10 | 😇 & 😬 |
| 5D | 11:55 PM, 15 April | SystemVerilog ALU – Part D | 18 | 😇 |
| 5E | 11:55 PM, 22 April | SystemVerilog ALU – Part E | 7 | |
| 5∞ | 11:55 PM, 25 April | SystemVerilog ALU | 15 | |
| 6 | 5:10 PM, 15 April | Unix crashes with processes | 10 | |
| 7 | 5:10 PM, 25 March | MIPS 32 exceptions | 10 | |
| 8 | 5:10 PM, 24 March | Gate multiplier | 10 | |
| 9 | 5:10 PM, 21 April | Power management | 10 | |
| 10 | 5:10 PM, 12 April | Memory | 15 | 😇 |
| 11 | 5:10 PM, 12 April | x64-64 assembly | 5 | 😇 |
| 12 | complete in-class, 12 April | You Have To Draw It! | 5 |