module hw5c_tb ;

      logic        CLOCK ;
      logic  [6:0] INSTRUCTION ;
      logic [15:0] INPUT ;
      logic  [2:0] STATUS ;
      logic [15:0] OUTPUT ;

      SerialALU dut(CLOCK, INSTRUCTION, INPUT, STATUS, OUTPUT) ;
      
      task just_do_it(
         logic  [1:0] test_source,
	 logic  [1:0] test_target,
         logic [15:0] test_input,
         logic [15:0] expected_output) ;

        INSTRUCTION = {3'b111, test_source, test_target}  ;
        INPUT = test_input ;
        #100
        $display("%7b, %16b --> %16b",
              INSTRUCTION, INPUT, OUTPUT) ; 
        assert (OUTPUT == expected_output) 
            else $error("Wrong output: %16b <> %16b", OUTPUT, expected_output, ) ;
      endtask 
      


/*
      always
      begin
        #100 clk = 0 ;
        #100 clk = 1 ;
      end
*/
      
      initial
      begin
        logic [15:0] register [1:3] ;
        logic [15:0] the_year ;
        register[1] = 16'd320 ;
        register[2] = 16'hbeef ;
        register[3] = 16'hfade ;
        the_year = 16'd2016 ;
        just_do_it(0, 0, the_year, the_year^the_year) ;
        just_do_it(1, 0, the_year, register[1]^the_year) ;
        just_do_it(2, 0, the_year, register[2]^the_year) ;
        just_do_it(3, 0, the_year, register[3]^the_year) ;
        just_do_it(0, 1, the_year, register[1]^the_year) ;
        just_do_it(0, 2, the_year, register[2]^the_year) ;
        just_do_it(0, 3, the_year, register[3]^the_year) ;
        just_do_it(1, 1, the_year, register[1]^register[1]) ;
        just_do_it(2, 2, the_year, register[2]^register[2]) ;
        just_do_it(3, 3, the_year, register[3]^register[3]) ;
        just_do_it(1, 3, the_year, register[1]^register[3]) ;
        just_do_it(2, 1, the_year, register[2]^register[1]) ;
        just_do_it(3, 2, the_year, register[3]^register[2]) ;
        $stop ;
      end
      
endmodule // end of module