This is a lab *experience*. There will be no grade for this lab.

It is mostly to give those who did *not* use
Logisim last semester, a chance
to refresh their skills.

If you’ve never used Logisim or have forgotten everything you know about it, you should review Tasks 1 to 4 of the CSCI 255 Introducing Logisim lab.

## The truth table of interest

Here’s the truth table for a modulo-3 adder. Notice the use of don’t cares.

inputs | outputs | ||||
---|---|---|---|---|---|

a_{1} | a_{0} | b_{1} | b_{0} | s_{1} | s_{0} |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 0 | 1 | 0 | 1 |

0 | 0 | 1 | 0 | 1 | 0 |

0 | 0 | 1 | 1 | x | x |

0 | 1 | 0 | 0 | 0 | 1 |

0 | 1 | 0 | 1 | 1 | 0 |

0 | 1 | 1 | 0 | 0 | 0 |

0 | 1 | 1 | 1 | x | x |

1 | 0 | 0 | 0 | 1 | 0 |

1 | 0 | 0 | 1 | 0 | 0 |

1 | 0 | 1 | 0 | 0 | 1 |

1 | 0 | 1 | 1 | x | x |

1 | 1 | 0 | 0 | x | x |

1 | 1 | 0 | 1 | x | x |

1 | 1 | 1 | 0 | x | x |

1 | 1 | 1 | 1 | x | x |

In this implementation
numbers from 0 to 2 are encoded in binary as two bits `0b00`

to `0b10`

(using the Java 7 notation).
We are assuming the 3, `0b11`

, never occurs. This allows us to use
don’t cares for 7 of the 16 possible input combinations.

In the usual digital logic notation, this can be expressed as follows:

- s
_{1}(a_{1},a_{0},b_{1},b_{0}) = Σ(2,5,8) + d(3,7,11,12,13,14,15) - s
_{0}(a_{1},a_{0},b_{1},b_{0}) = Σ(1,4,10) + d(3,7,11,12,13,14,15)

## Stuff to do

First, using Karnaugh maps, derive a boolean expression to implement the modulo-3 adder.

Second, start up Logisim and use the circuit analyzer to implement
this boolean expression in a subcircuit called `Add3`

.
Start by defining input pins `A1`

, `A0`

,
`B1`

, `B0`

and output pins for `S1`

and `S0`

in your subcircuit.
Then use the Analyze Circuit
feature of Logisim
to generate the circuit.
(See Task 4 of the
Introducing
Logisim lab for more information.)

Third,
use the almost-impossible-to-use
*splitters* of Logisim to modify your circuit so that its input
is *two* pairs of wires, called
`in0`

and `in1`

, and its output is *one*
pair of wires,
called `out`

.
Be sure to change the pins to have a data width of two.

Fourth,
make a new subcircuit called `Inc3`

.
The subcircuit `Inc3`

should have a input port called
`in`

and an output port
called `out`

. Both will have a data width of two.
`Inc3`

receives a two-bit input and increments it
modulo-3. This means in Java-speak that
`Inc3`

(`x`) is something like
`Add3`

(`x`,1).
Do *not* just copy your implementation of `Add3`

to `Inc3`

.
Use `Add3`

as a subcomponent, just
as you would have one method call another in Java. All you have to
do is “pass” a constant 1.

Fifth,
make a third subcircuit called `Count3`

.
This circuit will have a clock input port `clock`

.
and an output port called `out`

.
On clock *ticks*, this ciruit will count from 0 to 2 using
modulo-3 addition (0,1,2,0,1,2,0,1,2, …).
`Count3`

should be built with a two-bit register and an
single “instance” of

.
There’s really only one legal way to wire
these two components together.
`Inc3`