LC-3 Data Path Illustrated

• Start of fetch cycle
  • tri-state buffer
    • One of many driving a 16-bit wide bus
    • At most one must be active in any clock cycle
    • Octal Buffer/Line Driver with TRI-STATE® Outputs
  • register
    • Used to hold 16-bit values
    • Loads with LD input is asserted
    • 8-Bit Register
  • multiplexer
    • Used to choose between several input sources
    • With n selectors bits, chooses from 2ⁿ sources
    • Dual 4-Line to 1-Line Data Selectors/Multiplexers
• Reading from memory
  • memory
    • About 8192 words of 16-bit memory
    • Memories are composed of several n bit words
    • Expect memory enable and read/write selectors
    • With n address bits, memory may contain 2ⁿ words
    • 256 Bit TRI-STATE® Random Access Read/Write Memory
• Loading instruction into IR
• Decoding an instruction
  • Decoder
    • n input bits and 2ⁿ output bits
    • 3-to-8 and 2-to-2 Decoders/Demultiplexers
• Evaluate address -- PC offset
• Evaluate address -- Register offset
• ADDing two registers and storing result
  • Registers
    • Like small memories
    • But much faster
    • Usually have several ports for concurrent read/write operations
  • ALU
    • Receive operands and produce results
    • Control bits select operation to be performed
      • ADD
      • AND
      • NOT
      • pass through
    • 4-Bit Arithmetic Logic Unit
• ADDing registers and immediate value
• Writing to memory
• Loading destination register