module fsmlab(input  logic clk, 
              input  logic reset, 
              input  logic i,
              output logic o);

  typedef enum logic [2:0] {A, B, C, D, E} statetype;
  statetype state, nextstate;

  // state register
  always_ff @(posedge clk, posedge reset)
    if (reset) state <= A ;
    else       state <= nextstate ;

  // next state logic
  always_comb
    case (state)
      A: if (i) nextstate <= B ;
         else   nextstate <= A ;
      B: if (i) nextstate <= B ;
         else   nextstate <= C ;
      C: if (i) nextstate <= D ;
         else   nextstate <= A ;
      D: if (i) nextstate <= E ;
         else   nextstate <= C ;
      E: if (i) nextstate <= B ;
         else   nextstate <= C ;
      default:  nextstate <= A ;
    endcase

  // output logic
  assign o = (state == E);
endmodule