module bitparts
      (input    logic       a,
       input    logic [1:0] b,
       input    logic [2:0] c,
       output   logic       u,
       output   logic [1:0] v,
       output   logic [2:0] w,
       output   logic [3:0] x,
       output   logic [4:0] y,
       output   logic [5:0] z
      ) ;

     assign u = c ;
     assign {v,w[1]} = b ;
     assign {w[0],w[2]} = b ;
     assign x = {a, b} ;
     assign y = {b, 2'b00, b} ;
     assign z = c + 2'b11 ;
  
endmodule


/*
 After setting
    a:    1
    b:    11
    c:    111
 Result is
    u:    1
    v:    01
    w:    111
    x:    0111
    y:    10011
    z:    001010
*/