module divideby3FSM (input  logic clk, 
                     input  logic reset, 
                     output logic q);
   logic[1:0] count, nextcount ;
 
   // state register
   always_ff @ (posedge clk, posedge reset)
      if (reset) count <= 0;
      else       count <= nextcount;

   // next state logic
   always_comb
     if (count >= 2)
       nextcount <= 0 ;
     else
       nextcount <= count + 1 ;

   // output logic
   assign q = (count == 0);
endmodule