library IEEE ;
use IEEE.STD_LOGIC_1164.all ;
USE ieee.std_logic_unsigned.all;

-- Neither input or output
entity testfulladder is
end testfulladder ;

-- actual test bench
architecture fulladdertester of testfulladder is
  component fulladder
      port(
        An: in STD_LOGIC ;
        Bn: in STD_LOGIC ;
        Cn: in STD_LOGIC ;
        Cnp1: out STD_LOGIC ;
        Sn: out STD_LOGIC) ;
  end component ;

  signal vin  : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ;
  signal vout : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
  
  begin
    dut: fulladder port map(
       An => Vin(2), 
       Bn => Vin(1),
       Cn => Vin(0),
       Cnp1 => Vout(1),
       Sn => Vout(0)) ;
    
    process begin
      wait for 100 ps ;
      vin <= vin + "1" ;
    end process ;
  end ;