module lab4tb() ;
   logic clk, reset, left, right ;
   logic la, lb, lc, ra, rb, rc ;
   int i ;
   
   lab4 dut(clk, reset,
            left, right,
            la, lb, lc, ra, rb, rc) ; 
 
   initial begin
     reset = 1 ; #100 ;
     reset = 0 ; #100 ;
     left = 0 ; right = 0 ; #100 ;
     for (i=0; i<4; i=i+1)
     begin
        clk = 1 ; #100 ;
        if (la || lb || lc || ra || rb || rc)
          $error("lights should be off") ;
        clk = 0 ; #100 ;
        if (la || lb || lc || ra || rb || rc)
          $error("lights should be off") ;
     end
     left = 1 ;     #5 ;
     clk  = 1 ;    #95 ;
     for (i=0; i<4; i=i+1)
     begin
        clk = 1 ; #100 ;

        clk = 0 ; #100 ;

     end
  end
      
endmodule