Do the task described in the Spring 2003 ENGR/ECE 212 E-homework 1 assignment.
Due Tuesday May 13.
There is a choice here.
Your first option is to do the task described in the original Spring 2003 ENGR/ECE 212 E-homework 2. This involves the construction of a circuit using MSI components on a bread board.
The second option is to implement the 2-bit ripple carry adder as described in NCSU's Elecronic Homework Assignment on a break board.
The third option is to implement the 2-bit ripple carry adder
as described in
NCSU's
Elecronic Homework Assignment
in VHDL
Here's a VHDL example that might be of some
use in this task. This example compares the
number of bits that are "on" in two two-bit words.
The POPULATION function used here is based on
Wakerly's CONV_INTEGER function.
You want to use CONV_INTEGER.
library ieee ;
use ieee.std_logic_1164.all ;
entity POP2BIT is
port (
A : in STD_LOGIC_VECTOR (0 to 1);
B : in STD_LOGIC_VECTOR (0 to 1);
GT : out STD_LOGIC;
LT : out STD_LOGIC
) ;
end POP2BIT ;
architecture POP2BIT_arch_jdb of POP2BIT is
function POPULATION (X: STD_LOGIC_VECTOR) return INTEGER is
variable RESULT : INTEGER ;
begin
RESULT := 0 ;
for i in X'range loop
case X(i) is
when '1' | 'H' => RESULT := RESULT + 1;
when others => null;
end case;
end loop; -- i
return RESULT;
end POPULATION ;
begin -- POP2BIT_arch_jdb
GT <= '1' when POPULATION(A) > POPULATION(B)
else '0' ;
LT <= '1' when POPULATION(A) < POPULATION(B)
else '0' ;
end POP2BIT_arch_jdb;
I suggest you use the free VHDL Simili program of Symphony EDA to solve this problem. The free version can easily handle a problem of this size. It's only serious limitation is that it doesn't support debugging. VHDL Simili can be downloaded from Symphony EDA's web site
Here is a copy of a VHDL testbench problem that can be used to test your solution to E-Homework 2.
library ieee ;
use ieee.std_logic_1164.all ;
entity EHOME2_tb is
generic (whocares : boolean := true) ;
end EHOME2_tb ;
architecture TESTBENCH of EHOME2_tb IS
component EHOME2 IS
port (
X : in STD_LOGIC_VECTOR (2 downto 1);
Y : in STD_LOGIC_VECTOR (2 downto 1);
Cin : in STD_LOGIC ;
S : out STD_LOGIC_VECTOR (2 downto 1) ;
Cout : out STD_LOGIC
) ;
end component ;
constant period : time := 200 ns ;
signal TestX : STD_LOGIC_VECTOR (2 downto 1) ;
signal TestY : STD_LOGIC_VECTOR (2 downto 1) ;
signal TestCin : STD_LOGIC_VECTOR (1 downto 1) ;
signal TestS : STD_LOGIC_VECTOR (2 downto 1) ;
signal TestCout : STD_LOGIC_VECTOR (1 downto 1) ;
function CONV_STD_LOGIC_VECTOR(ARG: integer; SIZE: integer)
return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE downto 1) ;
variable temp: integer ;
begin
temp := ARG ;
for i in 1 to SIZE loop
if (temp mod 2) = 1 then
result(i) := '1' ;
else
result(i) := '0' ;
end if ;
temp := temp / 2 ;
end loop ;
return result ;
end ;
begin -- TESTBENCH
TestMod: EHOME2
port map (
X => TestX ,
Y => TestY ,
Cin => TestCin(1) ,
S => TestS ,
Cout => TestCout(1)
) ;
TestLoop: process
begin
while (true) loop
for i in 0 to 3 loop
TestX <= CONV_STD_LOGIC_VECTOR(i, 2) ;
for j in 0 to 3 loop
TestY <= CONV_STD_LOGIC_VECTOR(j, 2) ;
for k in 0 to 1 loop
TestCin <= CONV_STD_LOGIC_VECTOR(k, 1) ;
wait for period ;
end loop ;
end loop ;
end loop ;
end loop ;
end process ;
end TESTBENCH;
Although I have used functions to convert between VHDL
STD_LOGIC_VECTORs and integers,
you may find it easier just to use ordinary Boolean
logic operators in your solution
Due Tuesday May 13.
Do Raleigh's Electronic Homework 3 in ABEL or VHDL.
Here are two examples of ABEL programs that solve Problem 2B of Homework 6.
The first example uses ABEL's state machine description construct,
state_diagram.
" Implementation of problem using a state diagram
module HM6P2Bx
Title 'ENGR 212 Homework 6 Problem 2B'
Clock PIN ;
Reset PIN ;
x1 PIN ;
x2 PIN ;
z1 PIN istype 'COM' ;
z2 PIN istype 'COM' ;
Q1, Q2 PIN istype 'reg' ;
SREG = [Q1, Q2] ;
" You could choose anything you want here
A = [0,0];
B = [1,0];
C = [1,1];
D = [0,1];
equations
[Q1,Q2].AR = Reset;
[Q1,Q2].CLK = Clock;
state_diagram SREG
state A:
z1 = 0 ;
z2 = 1 ;
if (!x2) then A
else if x1 then B
else C ;
state B:
z1 = 0 ;
z2 = 1 ;
if x2 then C
else if x1 then B
else A ;
state C:
z1 = 1 ;
z2 = 0 ;
if x2 then C
else if !x1 # (x1 & x2) then D
else C ;
state D:
z1 = 1 ;
z2 = 0 ;
if x2 then B
else A ;
end HM6P2Bx
The second example uses ABEL's registered assignment operator
":=" to set the new state for state variables
Q2 and Q1.
" Implementation of problem using next state equations module HM6P2Bz Title 'ENGR 212 Homework 6 Problem 2B' Clock PIN ; Reset PIN ; x1 PIN ; x2 PIN ; z1 PIN istype 'COM' ; z2 PIN istype 'COM' ; Q1, Q2 PIN istype 'reg' ; SREG = [Q1, Q2] ; A = [0,0]; B = [1,0]; C = [1,1]; D = [0,1]; equations [Q1,Q2].AR = Reset; [Q1,Q2].CLK = Clock; Q1 := (!Q1 & x2) # (!Q2 & x2) # (Q1 & x1 & !x2) ; Q2 := (Q1 & Q2) # (Q1 & x2) # (!Q2 & !x1 & !x2) ; z1 = Q2 ; z2 = !Q1 & !Q2 ; end HM6P2Bz
For those who prefer VHDL, here is a program that solves a recent exam problem. Its output value obeys the unusual clocking requirements of the NC State assignment.
library ieee ;
use ieee.std_logic_1164.all ;
entity EXAM3PROB4 is
port (
Reset: in STD_LOGIC;
Clock: in STD_LOGIC;
SerIn: in STD_LOGIC;
SerOut: out STD_LOGIC
);
end EXAM3PROB4 ;
architecture EXAM3PROB4_arch_jdb of EXAM3PROB4 is
type state_type is (A, B, C) ;
signal e3p4state : state_type := A ;
begin
state_machine: process(Clock, Reset)
begin
if Reset = '1' then
e3p4state <= A ;
elsif Clock'event and Clock = '1' then
case e3p4state is
when A =>
SerOut <= '0' ;
if SerIn = '0' then
e3p4state <= A ;
else
e3p4state <= B ;
end if ;
when B =>
SerOut <= '0' ;
e3p4state <= C ;
when C =>
SerOut <= '1' ;
if SerIn = '0' then
e3p4state <= A ;
else
e3p4state <= B ;
end if ;
end case ;
end if ;
end process ;
end EXAM3PROB4_arch_jdb ;
Finally, here's a very long VHDL program for testing your solution.
library ieee ;
use ieee.std_logic_1164.all ;
entity EHOME3_tb is
generic (whocares : boolean := true) ;
end EHOME3_tb ;
architecture TESTBENCH of EHOME3_tb is
component EHOME3 is
port (
Reset: in STD_LOGIC;
Clock: in STD_LOGIC;
SerIn: in STD_LOGIC;
SerOut: out STD_LOGIC
);
end component ;
constant period : time := 200 ns ;
signal TestReset : STD_LOGIC ;
signal TestClock : STD_LOGIC ;
signal TestSerIn : STD_LOGIC ;
signal TestSerOut : STD_LOGIC ;
begin -- TESTBENCH
TestMod: EHOME3
port map (
Reset => TestReset ,
Clock => TestClock ,
SerIn => TestSerIn ,
SerOut => TestSerOut
) ;
TestDrive: process
begin
TestReset <= '0' ;
while true loop
for i in 0 to 10 loop
for j in 0 to 3 loop
wait for period/2 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
end loop ;
for j in 0 to 3 loop
wait for period/2 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '1' ;
wait for period/4 ;
TestClock <= '1' ;
end loop ;
end loop ;
wait for period/4 ;
TestReset <= '1' ;
wait for period/4 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
wait for period/4 ;
TestReset <= '0' ;
wait for period/4 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
for i in 0 to 7 loop
for j in 0 to 5 loop
wait for period/2 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
end loop ;
for j in 0 to 3 loop
wait for period/2 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '1' ;
wait for period/4 ;
TestClock <= '1' ;
end loop ;
end loop ;
wait for period/4 ;
TestReset <= '1' ;
wait for period/4 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
wait for period/4 ;
TestReset <= '0' ;
wait for period/4 ;
TestClock <= '0' ;
wait for period/4 ;
TestSerIn <= '0' ;
wait for period/4 ;
TestClock <= '1' ;
end loop ;
end process ;
end TESTBENCH ;