abl2edif:  version C.16 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.

	Input   : D:\Fndtn\Active\PROJECTS\TRY01\FSM01.abl
	Design  : FSM01
	Family  : XC3000
	Strategy: mod
	Optimize: balance
	Output  : D:\Fndtn\Active\PROJECTS\TRY01\FSM01.edn


Xabel Executing...
ahdl2blf FSM01.abl -mod FSM01 -ojhd compile -err FSM01.err
AHDL2BLF  ABEL-HDL Processor
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
blifopt FSM01.bl0 -o FSM01.bl1 -red bypin choose -collaps -err FSM01.err
BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
blif2eqn FSM01.bl1 -o FSM01.eq1 -err FSM01.err
BLIF2EQN  Open-ABEL Report Generator
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
bliflink FSM01.bl1 -o FSM01.bl2 -omod FSM01 -err FSM01.err
BLIFLINK  Top-Down Design Linker
ABEL 6.40 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
blif2eqn FSM01.bl2 -o FSM01.eq2 -err FSM01.err
BLIF2EQN  Open-ABEL Report Generator
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
blifopt FSM01.bl2 -o FSM01.bl3 -red bypin choose -collaps -err FSM01.err
BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
diofft FSM01.bl3 -o FSM01.bl4 -idev fpga -dev xc_mod -err FSM01.err
DIOFFT  Flip-Flop Transformation program
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.



DIOFFT complete. - Time 1 seconds


Xabel Executing...
blif2eqn FSM01.bl4 -o FSM01.eq3 -err FSM01.err
BLIF2EQN  Open-ABEL Report Generator
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
pifg_xa FSM01.bl4 -o FSM01.if -err FSM01.err
pifg_xa  Property Intermediate Form Generator (XABEL) by Synario Design
Automation.
ABEL 6.40 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.

Xabel Executing...
blif2net FSM01.bl4 -o FSM01.edn -str mod -inc FSM01.if -idev
d:\Fndtn\data\xlnxlib\xlnx_edf.rul -lib d:\Fndtn\data\xlnxlib -err FSM01.err
ref_2_inst: dangling port CLK of symbol fsm01
ref_2_inst: dangling port RST of symbol fsm01
ref_2_inst: dangling port SerIn of symbol fsm01
ref_2_inst: dangling port SerOut of symbol fsm01
Blif2Net  Open-Abel 2 To Netlist Translator
 2.30 Copyright (c) 1997-1999 Xilinx, Inc. All rights reserved.
Acknowledgments:
    This program is based on MISII, a UC Berkeley optimization tool.


abl2edif has succeeded. Please see the abl2edif.log for detailed information.