"
"  File:	D:\FNDTN\ACTIVE\PROJECTS\TRY01\FSM01.abl
"  created:	03/31/02 23:10:58
"  from:	'D:\FNDTN\ACTIVE\PROJECTS\TRY01\FSM01.asf'
"  by:		fsm2hdl - version: 2.0.1.53
"
module fsm01
Title 'fsm01'

Declarations

"clocks
CLK PIN;

"input ports
RST PIN;
SerIn PIN;

"output ports
SerOut PIN;

"******** SYMBOLIC state machine: Sreg0 ******
Sreg0 STATE_REGISTER;
Start, X1, X11 STATE;


"diagram ACTIONS

"************* state machine: Sreg0 *************

Equations
" clock signals definitions
	Sreg0.clk = CLK;

State_diagram Sreg0
	SYNC_RESET Start : RST;


State Start:
    
     IF (SerIn) THEN 
    X1 WITH
     SerOut = 0; 
     ENDWITH
     ELSE  IF (! SerIn) THEN 
        Start WITH
     SerOut = 0; 
     ENDWITH;


State X1:
    
     IF (SerIn) THEN 
    X11 WITH
     SerOut = 0; 
     ENDWITH
     ELSE  IF (! SerIn) THEN 
        Start WITH
     SerOut = 0; 
     ENDWITH;


State X11:
    
     IF (SerIn) THEN 
    X11 WITH
     SerOut = 0; 
     ENDWITH
     ELSE  IF (! SerIn) THEN 
        Start WITH
     SerOut = 1; 
     ENDWITH;

" end of state machine - Sreg0


end fsm01