--
--  File: D:\FNDTN\ACTIVE\PROJECTS\TRY00\FSM00.vhd
-- created: 03/31/02 23:16:52
--  from: 'D:\FNDTN\ACTIVE\PROJECTS\TRY00\FSM00.asf'
--  by fsm2hdl - version: 2.0.1.53
--
library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;
use SYNOPSYS.attributes.all;

entity fsm00 is 
  port (CLK: in STD_LOGIC;
        RST: in STD_LOGIC;
        SerIn: in STD_LOGIC;
        SerOut: out STD_LOGIC);
end;

architecture fsm00_arch of fsm00 is


-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (Start, X1, X11);
signal Sreg0: Sreg0_type;

begin
--concurrent signal assignments


Sreg0_machine: process (CLK, rst)

begin

if RST then
	Sreg0 <= Start;
elsif CLK'event and CLK = '1' then
	case Sreg0 is
		when Start =>
			if SerIn = '0' then
				Sreg0 <= Start;
			elsif SerIn = '1' then
				Sreg0 <= X1;
			end if;
		when X1 =>
			if SerIn = '1' then
				Sreg0 <= X11;
			elsif SerIn = '0' then
				Sreg0 <= Start;
			end if;
		when X11 =>
			if SerIn = '0' then
				Sreg0 <= Start;
			elsif SerIn = '1' then
				Sreg0 <= X11;
			end if;
		when others =>
			null;
	end case;
end if;
end process;

-- signal assignment statements for combinatorial outputs
SerOut_assignment:
SerOut <= '0' when (Sreg0 = Start and SerIn = '0') else
          0 when (Sreg0 = Start and SerIn = '1') else
          '0' when (Sreg0 = X1 and SerIn = '1') else
          '0' when (Sreg0 = X1 and SerIn = '0') else
          '1' when (Sreg0 = X11 and SerIn = '0') else
          '0' when (Sreg0 = X11 and SerIn = '1') else
          '0';

end fsm00_arch;