Problem 18. #define DFF_CK _LATB1 #define DFF_D _LATB2 #define DFF_S _LATB3 #define DFF_R _LATB4 #define DFF_Q _RB5 uint8 testDFFSync(uint8 u8_dval) { // setup DFF_S = 1; DFF_R = 1; DFF_CK = 0; DFF_D = 0; DELAY_US(1); // begin testing if (u8_dval) // set D value based in parameter value DFF_D = 1; // set D high else DFF_D = 0; // set D low DFF_CK = 1; // pulse the clock DELAY_US(1); DFF_CK = 0; DELAY_US(1); if (DFF_Q) // check the output return 1; // passed the test so return true else return 0; // failed the test so return false // shutdown: mostly not necessary DFF_S = 1; DFF_R = 1; DFF_CK = 0; DFF_D = 0; } Problem 20. #define GATE_A1 _LATB1 #define GATE_B _LATB2 #define GATE_Y _RB3 uint8 testGate(void) { uint8 i, j; // generate all input combinations using nested for-loops for (i = 0; i<=1; i++) { for (j = 0; j<=1; j++) { GATE_A = i; GATE_B = j; DELAY_US(1); // test output: XOR is a test for odd parity if ( GATE_Y == (GATE_A == GATE_B) ) // Y should be true when A != B return 0; // output was wrong so return false } } // all tests have been successfully completed so return true return 1; }