CSCI 255 Lab

Lab 4 -- Building Sequential Logic Components From Transistors

(The material in this lab was taken largely from a laborator exercise developed by W. J. Dally for "CS 99S: The Coming Revolution in Computer Architecture: What To Do With One Billion Transistors," a course offered at Stanford University in 2001.)


You will need the following equipment/components to create the circuits in today's lab:

Part 1: Rebuilding Your NAND Gate

The exercise that you worked for Lab 3 has been rewritten to give an exact specification and placement for each resistor. If you were unable to get your NAND gate to work, or even if your NAND gate did work, take another look at Exercise 3. Use the instructions in that lab exercise to guide the construction of a functional NAND gate with exact resistor placement. You will need a NAND gate with exactly that resistor configuration to successfully complete the remainder of this lab.


Show your NAND gate circuit to your instructor. Verify that the resistor configuration matches that specified in the revised Lab 3. Make sure that you have tested your NAND gate with all four input pairs before you call your instructor.  

Part 2: Introducing a Flip-Flop

The NAND gate that you've just built is a combinational logic circuit which means that the output depends only on the present state of the inputs. There are no feedback paths in combinational circuits: signals flow in one direction from the inputs to the outputs with no loops. If we add feedback to a logic circuit, we get a sequential logic circuit.

Sequential Logic

When you add feedback to a logic circuit, one of two things happens. If the feedback is unstable, it causes an oscillation. On the other hand, if the feedback is stable it holds the state of the circuit after the inputs are removed. In either case, we call the circuit a sequential logic circuit because the output now depends on the sequence or history of inputs and not just on the present combination of the inputs.


The circuit above (called a gated ring oscillator) is an example of a circuit with unstable feedback. When input a is high the circuit will oscillate rapidly producing alternating 1s and 0s on output x. To see that the circuit is unstable, cut the feedback loop from X to the NAND gate. The truth table for the circuit with the feedback cut is shown above; X corresponds to the input of the NAND gate and next X corresponds to the output. If the upper input of the NAND is 1, it will cause the output to go to 0, so we say that X=1 leads to next X = 0. Similarly, if the upper input of the NAND is 0, it will cause the output to go to 1. Thus X will not settle to a stable value, but will oscillate as long as a is high. In general, a feedback loop with inversion around the loop is unstable.

RS flip-flop

The circuit above, called a flip-flop, has stable feedback. To see this, break the feedback loop from X to the input of the AND gate. When s is low and ~r is high a 1 on the input of the AND will give a 1 on X, and a 0 on the input of the AND will give a 0 on X. The output is stable, but depends on the present state of the circuit in addition to the inputs. X is a state variable of this circuit.

We can write a truth table for the output of the flip-flop in terms of its inputs and its state variable by breaking the feedback loop at the state variable. The truth table for this flip-flop, using * to denote "don't care," is also shown above. Note that the flip-flop is reset (X set to 0) when ~r = 0, and is set ( X set to 1) when s = 1 otherwise it holds its previous state. Setting ~r=0 and s=1 is not allowed.

The panel above depicts a flip-flop made from an AND and an OR gate, but flip-flops are typically built around pairs of cross-coupled inverting elements such as NAND or NOR gates. The schematic below depicts an RS flip-flop.


The inputs are generally designated "S" and "R" for "Set" and "Reset" respectively. The name "flip-flop" arises because the circuit "flips" on if it gets one signal (the "Set" signal) and off if it gets another signal (the "Reset" signal). Your first job is to create the truth table for the RS flip-flop shown above. Start by writing down the truth table for a NAND gate. If you need help generating the truth table for the RS flip-flop, go to E. J. Mastascusa's discussion of that process.


Show your flip-flop truth table to your instructor.  

Part 3: Building a Flip-Flop

During your work in Part 2, you noticed a few interesting things:

  1. The flip-flop output Q is "set" or goes to 1 when the (S)et input is low, and the output resets or goes to 0 when the (R)eset signal is low. For this reason, the R and S inputs are often shown as inverted, as shown below.
  2. Setting both inputs to 0 causes both outputs to go to 1, which violates the Q/~Q behaviour. Therefore it is forbidden to have both inputs at a logic 0 level at the same time.
  3. The most interesting aspect of the flip-flop behavior occurs when both inputs are 1. In this configuration, the flip-flop holds it's previous state. It is this action that makes the flip-flop a primative memory element. It stores it's state (one bit of information) when both inputs are set to 1.

Now let's build a RS flip-flop using the NAND gates that you constructed in Lab 3 (and reconstructed at the beginning of this exercise). Work in teams of four---two teams of two where each team has one NAND gate to contribute to the effort. Each team of four can build one flip-flop by connecting the output of one NAND gate to the input of the other NAND gate as shown in the schematic above.

In order for your two NAND gates to work together as one flip-flop, they must be as similar as possible. They must not only have the same resistors at the same positions, they should also share a common power supply---use one power supply to power both NAND gates.

Test your flip-flop and make sure that it performs as expected using the truth table that you developed in Part 2.


Show your flip-flop to your instructor.