Other Verilog stuff

Events in Verilog history

Before there were hardware description languages, designers used an informal notation called register transfer language or RTL. It has even been used in CSCI 255 / ECE 109 to specify the implementation of a very simple computer.

Here is a list of the Verilog standards. These are managed by Accellera System Initiative, which was formed from a merger of the Verilog, VHDL & SystemC specification groups.

• Verilog-95 — IEEE 1364-1995
• Verilog-2001 — IEEE 1364-2001
  • Probably, still the most commonly used standard
  • Addition of signed variables to Verilog-95
• Verilog-2005
  • Few changes other than new math functions
• SystemVerilog-2005 — IEEE 1800-2005
  • major extensions (535 pages worth)
  • Incorporation of SystemC for simulation
• SystemVerilog-2009 — IEEE 1800-2008
  • Merger of Verilog and SystemC
  • No more extensions to Verilog
  • VPI (Verilog Procedural Interface) allows call of C functions
• SystemC standard – IEEE 1666-2011
  • 614 pages of documentation
• SystemVerilog-2012 — IEEE 1800-2012
  • 1315 pages of documentation
• Altera Cyclone V
• FPGA architecture

Why is this so hard?

Testing your circuit by stepping through it manually or creating a stimulus waveform or running a stimulus control program or tcl isn’t enough. You need both an HDL (Hardware Description Language) for synthesizable code and HVL (Hardware Verification Language) for executable code such as SystemVerilog. Or you could use an HDL that can interface with “conventional” programming languages, like C++, using something like SystemVerilog DPI.

Also, where are some good, widely used, unit testing packages such as JUnit or CppUnit or QUnit?

Implementation styles in SystemVerilog

Structural implementation of a full adder

module fulladder(
   input logic An,    // A bit
   input logic Bn,    // B bit
   input logic Cn,    // carry-in bit
   output logic Cnp1, // carry-out bit
   output logic Sn) ; // sum bit

      logic tAB, tAC, tBC ;        // wires leaving the AND gates

      xor(Sn, An, Bn, Cn) ;
      and(tAB, An, Bn) ;
      and(tAC, An, Cn) ;
      and(tBC, Bn, Cn) ;
      or(Cnp1, tAB, tAB, tBC) ;

endmodule

Structural implementation of a full adder with named gates

module fulladder(
   input logic An,    // A bit
   input logic Bn,    // B bit
   input logic Cn,    // carry-in bit
   output logic Cnp1, // carry-out bit
   output logic Sn) ; // sum bit

      logic tAB, tAC, tBC ;        // wires leaving the AND gates

      xor  sum(Sn, An, Bn, Cn) ;
      and  abTerm(tAB, An, Bn) ;
      and  acTerm(tAC, An, Cn) ;
      and  bdTerm(tBC, Bn, Cn) ;
      or   carry(Cnp1, tAB, tAC, tBC) ;

endmodule

Behavioral implementation of a full adder

module fulladder(
   input logic An,    // A bit
   input logic Bn,    // B bit
   input logic Cn,    // carry-in bit
   output logic Cnp1, // carry-out bit
   output logic Sn) ; // sum bit

      assign Sn = An ^ Bn ^ Cn ;
      assign Cnp1 = An & Bn | An & Cn | Bn & Cn ;

endmodule

Behavioral implementation of a full adder using addition with vector

module fulladder(
   input logic An,    // A bit
   input logic Bn,    // B bit
   input logic Cn,    // carry-in bit
   output logic Cnp1, // carry-out bit
   output logic Sn) ; // sum bit

     logic[1:0] sum2bit ;
     assign sum2bit = An + Bn + Cn ;
     assign Sn = sum2bit[0] ;
     assign Cnp1 = sum2bit[1] ;

endmodule

Behavioral implementation of a full adder using addition with {}

module fulladder(
   input logic An,    // A bit
   input logic Bn,    // B bit
   input logic Cn,    // carry-in bit
   output logic Cnp1, // carry-out bit
   output logic Sn) ; // sum bit

     logic {Cnp1, Sn} = An + Bn + Cn ;

endmodule

Behavioral implementation of a full adder tattoo

This tattoo is mentioned in a Discover blog.

The program is taken from the textbook.

// 4.7: fulladder

module fulladder(input  logic a, b, cin, 
                 output logic s, cout);

  logic p, g;

  assign p = a ^ b;
  assign g = a & b;
  
  assign s = p ^ cin;
  assign cout = g | (p & cin);
endmodule

Other HDL programs

SystemC implementation

You can see the C++ (in)heritage in this example.

• Lab at UC-Riverside

VHDL implementation

You can see the Ada heritage in this example.

• Lab at UC-Riverside

MyHDL implementation

You can really see the Python.

• Four bit adder in MyHDL — look for fullAdder