CSCI 320 — Another testbench

A second look at ancient multiplication

• SystemVerilog for Verification by Chris Spear and Greg Tumbush
  • Data Types, chapter 2
  • Connecting the Testbench and Design
• Removing the clock generation from the testbench
  • Modified testbench
  • New test module

Modularization in testing

• Do you have a do_reset task?
• Do you have a do_state_transition task?
• How are you generating the clock?