- Microarchitecture (Chapter 7)
In modern terminology, chapter 6 discusses the instruction set architecture and chapter 7 discusses the microarchitecture. The “micro” has nothing to do with microcomputers.
Implementing a simplified microarchitecture in HDL was a popular activity in a computer architecture course. Generally the activity is restricted to a small part of a “toy” architecture. This is usually done by developing a data path and an associated FSM control structure. An early edition of the textbook Digital Design with an Introduction to the Verilog HDL was used by Wayne Lang in the Fall 1999 section of CSCI 255 following this example. Later offerings of CSCI 255 and ECE 109 used Introduction to Computign Systems: From Bits and Gates to C which presented a very detailed microprogrammed implementation which could be implemented in HDL but was usually accompished by filling in a table.
Notes on the PowerPoint
- Slide 5: It’s not about clock speed
- Slide 8: The programmer view of the single cycle implementation
- Slides 10–19: A well-illustrated at how the datapath
expands to implement an instruction
lw rt, imm(rs)
sw rt, imm(rs)
add rd, rs, rt
beq rs, rt, label
- Slides 20–33: The control
or rd, rs, rt
addi rt, rs, imm
beq rs, rt, label
- Slide 40: The modules of the multicycle implementation
- Slides 41–51: Another well-illustrated datapath
- Slides 52–67: Multicycle control
- Slides 75–76: Single vs Multi
- Slides 77–107: The pipelined implementation
- Slide 81: The control signal must be delayed until the data is available
- Slide 85: Remember the jump delay slots in CSCI 255?
- Slide 87: RAW (Read-After-Write) dependency
- Slide 88: Sometimes called scoreboarding
- Slide 89: Could be register or data memory
- Slide 94: Or it could be related to instructions
- Slide 101: Static or dynamic?
- Slide 107: SPEC
- Slides 108–114: Exceptions
Search for intel processor mask.