Chapter 5 comments

The PowerPoint

Digital Building Blocks (Chapter 5 except Section 3.5)

Notes on the PowerPoint

Slides 4–6: Full adder
Slides 8–9: Ripple-carry adder: O(n) time & O(n) space
Slides 10–14: Carry-lookahead adder
- 74181 ALU
- 74182 look-ahead carry generators
- If k = n^½, O(n^½) time & O(n) space
Slides 15–19: Prefix adder: O(log n) time & O(n log n) space
- Prefix address in spreadsheet
- formulas for prefix adder
  - P and G at the top
    - P_-1:-1 = 0
    - G_-1:-1 = c_i
    - P_{i:i_{= A_i B_i}}
    - G_i:_i = A_i + B_i
  - P and G in the middle
    - P_i:j = P_i:k P_k-1:j
    - G_i:j = G_i:k + P_i:k G_k-1:j
  - result at the bottom
    - S_i = G_i-1:-i &xor; A_i &xor; B_i
Slides 20–21: Adder performance with typical numbers
Slides 22–29: Typical ALU operations
Slides 30–33: Shifters
Slides 34–36: Multiply and divide
- Binary multiplication in C
- Gate array multiplication: Figure 5.18
- Divide and conquer — using a 16-bit gate multiplier for 32 bits
  - α = α_hi<<16 + α_lo
  - β = β_hi<<16 + β_lo
  - α×β = ((α_hi×β_hi)<<32) + ((α_hi×β_lo + α_lo×β_hi)<<16) + (α_lo×β_lo)
  - Better than O(n²)
    - A = α_hi×β_hi
    - B = α_lo×β_lo
    - C = (α_hi + α_lo) × (β_hi + β_lo)
    - C - A - B = α × β
- Binary shift-and-restore division in C
Slides 58–62: Counters and shifters
- Dual 4-bit counter
- 8-bit serial-in parallel-out shift register
Slides 63–68: Memory structure
Slides 69–71: RAM vs ROM
Slides 72–77: DRAM vs SRAM
- 8 Gb SDRAM
Slides 78–87: ROM
EEPROM
- 128-bit (16×8) I²C
- 1024K-bit (128k×8) I²C
Slide 88: Register files
- 16-by-4 register file
Slide 89: SystemVerilog memory
Slide 90: PLAs vs FPGAs
Slide 91–92: PLA
- PLA — Programmable Logic Array
- TICPAL22V10Z (44×132) PAL
- PLA vs PAL
Slide 93–100: FPGA
- CPLD such as Altera Max V
- FPGA such as Altera Cyclone V
- SoC such as Altera Cyclone V SoC
IP core
- OpenCores