- Sequential Logic Design (Chapter 4)
SystemVerilog — some odd parts
If you don’t declare a variable, the variable is a wire.
Legal programs may not compile
Few, if any Verilog/SystemVerilog/VHDL systems, will compile all programs. Even fewer will be synthesizable on any device. Even fewer will be synthesizable on the device you plan to use.
Wires and registers
Verilog supported two bit-level
caused great anguish for Verilog programmers. For the most part,
logic type of SystemVerilog, can be used in place
If you are worried about the differences, read the
UC-Berkeley CS150 handout
a useful stackoverflow posting
which explains the difference.
Packed vs unpacked
SystemVerilog (and Verilog) have packed and unpacked arrays. (These are very different than the packed structures of Pascal: Not that any of you have heard of that.) This results in declarations such as the following:
logic [11:0] addr ; // packed logic data [15:0] ; // unpacked logic [15:0] mem [1023:0] ; // unpacked collection of packed
Packed arrays are often called vectors.
A vector must be implemented as a contiguous set of bits and, for
that reason, must be constructed from bit-like types, such as
Often bit slices, such as
data[15:8] are used to
refer to part of a vector.
PS: It’s really much more complicated than this.
Equality and matching operators
In SystemVerilog, both
0 == x and
0 != x yield the value
0 === x yields 1 and
0 !== x yields
(This is very different from the
=== operator of
There is also wildcard equality which can be used to
With wildcard matching
z will match anything.
The means that both
2'b00 ==? 2'b0x and
2'b10 !=? 2'b0x yield
Wildcards only work in the right operand:
2'b0x ==? 2'b00 and
2'b0x !=? 2'b10 yield
(At least, I think that’s the case.)
SystemVerilog supports the logical implication,
and logical equivalence,
<->, beloved by
(Or, at least by those mathematicians who consider
z to be Boolean values.)
Truth tables, with don’t cares, can be implemened with a user defined primitive.
Named arguments to modules
Python allows values to be passed to function as either
saturate(A, lo, hi),
or keyword arguments, such as
saturate(vector=A, lowerbound=lo, upperbound=hi).
SystemVerilog does something similar with named and positional associations. In the introductory SystemVerilog lab the following example of positional association was used to connect the testbench to the device-under-test:
fulladder dut(vin, vin, vin, vout, vout) ;
However, this could also be done with name association:
fulladder dut( .An (vin), .Bn (vin), .n (vin), .Cnp1 (vout), .Sn (vout) ) ;
Name association is certainly a lot more verbose. However, computer
engineers tend to refer to ports with names, such as
rather than numbers, such as 5 for the 5’th connection.
A variable started with a backslash can contain any printable characters. These must be terminated by whitespace. Here are some examples:
This allows the SystemVerilog developer to use the exact same names used by the hardware people.
Building a computer
You can implement your own computer with an FPGA as a System on a chip. There are many open cores that allow this, or you can license an ARM Cortex-M1.
The Spring 2014 homework
Sometimes you need to think like a programmer.