CSCI 320 — Chapter 2 comments
The PowerPoint
FPGA development boards
Notes on the PowerPoint
- Slides 50–53:
X
and Z
- Standard CNF notation with don’t cares: f(a,b,c) = Σ(0, 3 5) + d(6, 7)
- Verilog has four logic values:
0
, 1
,
x
and z
- 16-bit TRI-STATE latch
- TRI-STATE® is a registered trademark of National Semiconductor
- Slides 63–65: Karnaugh map with don’t cares
- Implementing the high impedance state requires something like a
buffer
with 3-state outputs
- Slides 67–70: Multiplexers deja vu and LUTs
(look up tables)
- Slides 74–77: Time and delay
- Contamination delay
- Propagation delay
- Slides 75–82: Glitches and hazards