Turning it in
This assignment must be uploaded HW 3 on moodle by 5:10 PM on 12 February.
Do Exercise 4.32 (which builds on Exercise 3.22 which uses the FSM in Figure 3.69) from the textbook.
your solution for this homework must be a ZIPed copy of a ModelSim project stored in a directory named exer4.32. If you use the lab in RRO 223 to work on this project, you must use the following commands to create a read-protected directory for the project.
mkdir -p csci/320/exer4.32 chmod go-rwx csci/320/exer4.32
On Linux systems, the ZIP file can be created within the csci/320 directory with the following one-line command:
cd csci/320; zip -r exer4.32.zip exer4.32
Required module interface
Use the following module interface so that I can plug your design into my testbench.
module exer_4_32 (input logic clk, input logic reset, input logic a, input logic b, output logic q) ; // Your code goes here endmodule
A word about appropriate submissions
This is an individual assignment. Other than incorporating the module interface shown about, every character typed to generate this assignment must be typed by you!
You may talk with others about this assignment. However, this is not a “pair” programming exercise, so you should not be typing while talking.
SystemVerilog programming can be a little tedious. Your solution should have a resemblence to the one of Example 4.31 (p. 212).
A testbench is not required for this program; however, your program must compile successfully, and you should test it using the wave simulator.