Events in Verilog history
Before there were hardware description languages, designers used an informal notation called register transfer language or RTL. It has even been used in CSCI 255 to specify the implementation of a very simple computer.
Here is a list of the Verilog standard. These are managed by Accellera System Initiative, which was formed from a merge of the Verilog, VHDL & SystemC specification groups.
- Verilog-95 — IEEE 1364-1995
- Verilog-2001 — IEEE 1364-2001
- Probably, still the most commonly used standard
- Addition of signed variables to Verilog-95
- Few changes other than new math functions
- SystemVerilog-2005 — IEEE 1800-2005
- major extensions (535 pages worth)
- Incorporation of SystemC for simulation
- SystemVerilog-2009 — IEEE 1800-2008
- Merge of Verilog and SystemC
- No more extensions to Verilog
- VPI (Verilog Procedural Interface) allows call of C functions
- SystemVerilog-2012 — IEEE 1800-2012
The old-style flipflops and latches
These examples are taken from the first edition of the textbook.
module flop(input clk, input [3:0] d, output reg [3:0] q); always @(posedge clk) q <= d; endmodule
module latch(input clk, input [3:0] d, output reg [3:0] q); always @(clk, d) if (clk) q <= d; endmodule
In regular Verilog, you may encounter the
Confusing the two leads to much anguish and
In theory, a
wire is connection path or net and
reg is something else, perhaps even a register.
However, take a look at
reg for no less than sixteen
rules of how Verilog distinguishes the two.
SystemVerilog has a
logic declaration which can
be used in place of either
It seems to be a good move.
Verilog Modules, parameters & arguments
SystemVerilog modules look a bit like Java methods and C/C++ functions, but there are some significant differences.
First, the module definition is not surrounded by braces.
Instead the keyword
begins the module definition and the keyword
ends the definition.
macromodule is similar to an inline
functions of C++ or to the just-in-time
compiler optimizations made for
Java HotSpot virtual machine.
The statements of the
may be expanded in the body
of the caller.
macromodule is very rare.
parameterto configure modules using something similar to a run-time constant. Start with this example from your textbook.
module flop(input logic clk, input logic [3:0] d, output logic [3:0] q); always_ff @(posedge clk) q <= d; endmodule
This module only works with four-bit words.
However, by using
the example can be made to work with words of any size.
module flop #(parameter type regtype = logic [3:0]) (input logic clk, input regtype d, output regtype q); always_ff @(posedge clk) q <= d; endmodule
This is beginning to look like parameterized types in Java. We probably won’t do this in class; but, in case you are wondering, here is how you instantiate one of these parameterized modules.
flop #(.regtype(logic [15:0])) ff1( sysclk, statein, stateout) ;
Fourth, the real parameters of the module may be specified in two different styles. The difference between the two is similar to the difference between “old-style” C and ANSI C parameter declarations, but even more dated.
Here’s a repeat of the style used in the textbook.
module flop(input logic clk, input logic [3:0] d, output logic [3:0] q);
And here’s another way to list the parameters. The odd thing is that the parameters are declared in the same place as local variables.
module flop(clk, d, q) ; input logic clk ; input logic [3:0] d ; output logic [3:0] q ;
Fifth, as seen above, SystemVerilog does have
Also, modules do not return values like they do in C, C++,
Java and Python. They store their results into
output or even
Sixth, SystemVerilog does allow the passing of arguments by
names, rather than position. This practice is appearing in other
programming languages, particularly Python.
Here is an example of how the
flop module could
be instantiated using named arguments.
flop #(.regtype(logic [15:0])) ff1(.clk(sysclock), .q(stateout), .d(statein)) ;