This assignment must be uploaded in two files by 11:00 PM on 28 March to the homework 7 moodle page. One file will be a SystemVerilog testbench module named ancienttimestb.sv. The other will be a PDF or text file that justifies the testcases implemented in your testbench.
The task
Write a SystemVerilog testbench module
for the ancienttimes module you wrote for
Homework 6.
Use the following module header in your definition.
module ancienttimestb
#(parameter DATA_WIDTH = 12)
() ;
You should also turn in a couple of paragraphs that describes your testing strategy in writing this program. Describe the test cases you chose and state why your choices are complete and appropriate. This is similar to the discussion of testing strategy requested in some CSCI 181 assignments.
By the way, SystemVerilog does have a $urandom system
function that can be used to generate random values over a limited
range.