Problem: To recognize 01 repeated 31 times followed by 11, that is, 0101010101010101010101010101010101010101010101010101010101010111. Implementing this as a monolithic FSM is a bad idea. It would require 64 states and be very tedious to specify.
Add a counter module with three input "commands".
INCR | Add one to the COUNT |
HOLD | Hold the COUNT (add zero) |
CLEAR | Set COUNT to zero |
The counter should also have a single output C31
which is asserted when COUNT
is 31.
_____ | | INCR ---------->| | | | HOLD ---------->| |---------> C31 | | CLEAR ---------->| | |_____|
Use a 5-bit wide register,
a 5-bit wide half-adder,
and a multiplexer to implement this module.
The input of the register is chosen from one
of three sources: 00000 for CLEAR,
present value of COUNT for HOLD, and
output of half-adder (COUNT+1) for INCR.
The output of the Counter is the carry-out of the half-adder
Control FSM receives two inputs: (1), INP
, the
input from "outside" world, and (2), C31
, the
output of the counter.
It should produce two outpus: (1), OUT
, the
output to the "outside" world, and (2), CNTL
, the
control input of the counter.
The control FSM only has two states:
(1), M10*
,
which signifies that the previous input end with COUNT
sequences of 10; and
(2), M10*1
,
which signifies that the previous input end with COUNT
sequences of 10 followed by a single 1.
Here is its state table.
present state | outside input | counter output | next state | outside output | counter input | |
---|---|---|---|---|---|---|
M*Count | 0 | 0 | M*Count | 0 | CLEAR | COUNT is good |
M*Count | 0 | 1 | M*Count | 0 | CLEAR | COUNT is good |
M*Count | 1 | 0 | M*Count1 | 0 | HOLD | ends in 10... 1 |
M*Count | 1 | 1 | M*Count1 | 0 | HOLD | ends in 10.. 1 |
M*Count1 | 0 | 0 | M*Count | 0 | INCR | another 10, increment |
M*Count1 | 0 | 1 | M*Count | 0 | HOLD | another 10, hold at 31 |
M*Count1 | 1 | 0 | M*Count1 | 0 | CLEAR | Not enough 10's |
M*Count1 | 1 | 1 | M*Count | 1 | CLEAR | We did it! |