LC/3 microarchitecture

LC-3 data path

See Figure C-3 for the simplified LC-3 data path.

Data path control signals

Signal Name Signal Values Purpose
LD.MAR NO, LOAD Controls Memory Address Register
LD.MDR NO, LOAD Controls Memory Data Register
LD.IR NO, LOAD Controls Instruction Register
LD.BEN NO, LOAD Branch Enable
LD.CC NO, LOAD Controls Conditional Code
LD.PC NO, LOAD Controls Program Counter
GatePC NO, YES Places PC on bus
GateMDR NO, YES Places MDR on bus
GateALU NO, YES Places ALU output on bus
GateMARMUX NO, YES Places useful address on bus
ADDR1MUX PC+1, BaseR Selects base for address
ADDR2MUX ZERO, Offset6, Offset9, Offset11 Selects offset for address
MARMUX IR7..0, ADDER Used for TRAP instruction
PCMUX PC+1, BUS, ADDER Selects new value for PC
DR R0 to R7 Selects destination register
SR1 R0 to R7 Selects source register 1
SR2 R0 to R7 Selects source register 2
SR2MUX IR, SR2 Immediate or source operand
ALUK ADD, AND, NOT, PASSA ALU control
R WORKING, DONE Memory ready

Memory control signals

Signal Name Signal Values Purpose
MIO.EN NO, YES Enables memory operation
R.W RD, WR Selects read or write

Instruction cycle

Fetch

  1. Load MAR with PC and increment PC
  2. Wait for Instruction to appear in MDR
  3. Load IR with MDR

Decode

Examine IR[15:12] to select one of sixteen possible instructions.

Evaluate address

Determine memory address, if any, needed by the instruction.

Fetch operands

Obtain operands, if any, needed for the instruction.

Execute

May performs an ALU operation or update PC with branch target.

Store result

Stores the result in register or memory. Updates condition code if appropriate.

RTL -- Register Transfer Language -- by the clock

Add

  1. MAR ← PC & PC ← PC+1
  2. Initiate memory read & wait until memory ready
  3. IR ← MDR
  4. Decode IR[15..12] & set BEN (which will not be used)
  5. DR ← SR1 + Op2 & set NZP

Branch

  1. MAR ← PC & PC ← PC+1
  2. Initiate memory read & wait until memory ready
  3. IR ← MDR
  4. Decode IR[15..12] & set BEN (which will be used)
  5. Skip, if BEN is not set. Update PC, if BEN is set.

Load

  1. MAR ← PC & PC ← PC+1
  2. Initiate memory read & wait until memory ready
  3. IR ← MDR
  4. Decode IR[15..12] & set BEN
  5. MAR ← PC+Offset9
  6. Initiate memory read & wait until memory ready
  7. DR ← MDR & set NZP

Load indirect

  1. MAR ← PC & PC ← PC+1
  2. Initiate memory read & wait until memory ready
  3. IR ← MDR
  4. Decode IR[15..12] & set BEN
  5. MAR ← PC+Offset9
  6. Initiate memory read & wait until memory ready
  7. MAR ← MDR
  8. Initiate memory read & wait until memory ready
  9. DR ← MDR & set NZP

Controlling the data path

See Figure C.1 for a very abstract view of control and data. The actual implementation is encoded in a state machine (Figure C.2) which uses a microsequencer (Figure C.5) to select the next state where (1) J is the present state (number) of the controller, (2) IRD is asserted during instruction (register) decode, and (3) COND encodes branch enable and more exotic ways to select the PC.

Fill in the control store specification (Figure C.9) to complete the experience using the on-line copy of Appendix C.