See Figure C-3 for the simplified LC-3 data path.
Signal Name | Signal Values | Purpose |
---|---|---|
LD.MAR | NO, LOAD | Controls Memory Address Register |
LD.MDR | NO, LOAD | Controls Memory Data Register |
LD.IR | NO, LOAD | Controls Instruction Register |
LD.BEN | NO, LOAD | Branch Enable |
LD.CC | NO, LOAD | Controls Conditional Code |
LD.PC | NO, LOAD | Controls Program Counter |
GatePC | NO, YES | Places PC on bus |
GateMDR | NO, YES | Places MDR on bus |
GateALU | NO, YES | Places ALU output on bus |
GateMARMUX | NO, YES | Places useful address on bus |
ADDR1MUX | PC+1, BaseR | Selects base for address |
ADDR2MUX | ZERO, Offset6, Offset9, Offset11 | Selects offset for address |
MARMUX | IR7..0, ADDER | Used for TRAP instruction |
PCMUX | PC+1, BUS, ADDER | Selects new value for PC |
DR | R0 to R7 | Selects destination register |
SR1 | R0 to R7 | Selects source register 1 |
SR2 | R0 to R7 | Selects source register 2 |
SR2MUX | IR, SR2 | Immediate or source operand |
ALUK | ADD, AND, NOT, PASSA | ALU control |
R | WORKING, DONE | Memory ready |
Signal Name | Signal Values | Purpose |
---|---|---|
MIO.EN | NO, YES | Enables memory operation |
R.W | RD, WR | Selects read or write |
Examine IR[15:12] to select one of sixteen possible instructions.
Determine memory address, if any, needed by the instruction.
Obtain operands, if any, needed for the instruction.
May performs an ALU operation or update PC with branch target.
Stores the result in register or memory. Updates condition code if appropriate.
See Figure C.1 for a very abstract view of control and data. The actual implementation is encoded in a state machine (Figure C.2) which uses a microsequencer (Figure C.5) to select the next state where (1) J is the present state (number) of the controller, (2) IRD is asserted during instruction (register) decode, and (3) COND encodes branch enable and more exotic ways to select the PC.
Fill in the control store specification (Figure C.9) to complete the experience using the on-line copy of Appendix C.