UNCA ECE 406 -- Spring 2007

• Instructor: J. Dean Brock
• Meetings: W 8:30-10:20 and MW 3:45-5:00, as announced

This page is a brief index of all class handouts, particularly homework assignments, for UNCA course ECE 406.602, which is really the Asheville section of NCSU ECE 406-602, Design of Complex Systems.

This page can be accessed through the following URL:

• http://www.cs.unca.edu/ece406

Recent additions

Course links

Here are some links for syllabus, assignments, quizzes, and useful on-line class readings. As the semester continues more will appear.

• Syllabus
• Schedule and lecture notes
• Homework assignments
  1. Verilog Language Conventions and Structure -- Due 29 January
  2. Gate-Level Functional Modeling -- Due 7 February.
     Don't submit your Verilog code by Wolfware. Instead email it to brock@cs.unca.edu and turn in the written part of the assignment in class.
  3. Behavioral Modeling -- Due 14 February.
     Again email your Verilog, don't Wolfware it.
  4. Verilog Simulation (Lab Report Required), Modeling Sequential Designs -- Due 23 February.
     Again email your Verilog, don't Wolfware it. I hope you have better luck with your EOS account than the instructor is having.
  5. Logic Synthesis -- Due 28 March
  6. LC-3 Microcontroller -- Due April 4
  7. Homework 7 -- PIC -- due 7 May
  8. Homework 8 -- CAN -- due 7 May
• Projects
  1. LC-3 Microcontroller (Needed files: proj1.tar) -- Due April 9
  2. Project 2 -- JSRR 7 -- due 7 May
• Quiz answers
  • Some answers for Quiz 1
  • Some answers for Quiz 2
• Raleigh sections of ECE 406
  • Section 001 -- the big section
  • Section 002 -- the other section
• On-line Verilog manuals