- Instructor: J. Dean Brock
- Meetings: W 8:30-10:20 and MW 3:45-5:00, as announced

This page is a brief index of *all* class handouts,
particularly homework assignments,
for UNCA course ECE 406.602, which is really the
Asheville section of NCSU ECE 406-602,
Design of Complex Systems.

This page can be accessed through the following URL:

Here are some links for syllabus, assignments, quizzes, and useful on-line class readings. As the semester continues more will appear.

- Syllabus
- Schedule and lecture notes
- Homework assignments
- Verilog Language Conventions and Structure -- Due 29 January
- Gate-Level Functional Modeling -- Due 7 February.

Don't submit your Verilog code by Wolfware. Instead email it to`brock@cs.unca.edu`and turn in the written part of the assignment in class. - Behavioral Modeling -- Due 14 February.

Again email your Verilog, don't Wolfware it. - Verilog Simulation (Lab Report Required), Modeling Sequential Designs -- Due 23 February.

Again email your Verilog, don't Wolfware it. I hope you have better luck with your EOS account than the instructor is having. - Logic Synthesis -- Due 28 March
- LC-3 Microcontroller -- Due April 4
- Homework 7 -- PIC -- due 7 May
- Homework 8 -- CAN -- due 7 May

- Projects
- LC-3 Microcontroller (Needed files: proj1.tar) -- Due April 9
- Project 2 -- JSRR 7 -- due 7 May

- Quiz answers
- Raleigh sections of ECE 406
- On-line Verilog manuals