Spring 2007 ECE 406 Exam 2 Study Guide

Exam 2 is about Verilog, particularly all the "state" features not covered in Exam 1.

You should know how to:

1. Draw a schematic to match a Verilog program.
2. Draw a timing diagram to match a Verilog program.
3. Identify common errors in Verilog code:
   1. Improper use of wires and registers
   2. Incomplete sensivity lists
   3. Unintentional latches
   4. Unintentional "wired-or" logic
4. Write Verilog code to implement common combinational elements, such as multiplexors
5. Write Verilog code to implement common sequential elements, such as flip-flops and latches
6. Write Verilog code to implement a sequential circuit, typically specified as a finite state machine
7. Write Verilog code to implement a specific timing protocol, that is, that produces signals with a specific clock phase