- PLDs (programmable logic devices)
- PLAs
- PALs
- Introduced different sorts of "buffers" in context of PLDs
- non-inverting buffer
- buffers with dual complementary outputs
- tri-state buffers

- PLA nomenclature (
`n`x`m`PLA with`p`product terms) - Be able to implement combinational logic using PLAs

- "Active-high" and "active-low" signals
- "Enable" signals for MSI components (e.g., decoders)
- Binary Decoders
- Understand function, truth table, etc.
- Understand and be able to design logic for decoders
- Know the symbol for a decoder and how to use it
- Active-high and active-low enables and outputs
- Cascading decoders to build larger decoders (use chip enables)

- Multiplexors (MUXes)
- Understand function, truth table, etc.
- MUX nomenclature (
`b`-bit`N`:1 MUX) - Know the symbol for a MUX and how to use it
- Know how many select signals are required
- Understand and be able to design logic for MUXes
- Building larger MUXes out of smaller MUX building blocks
- Implementing arbitrary logic functions using a MUX

- XOR, XNOR gates
- Understand function, truth table, etc.
- Know symbols
- Know various implementations of XOR gate (AND-OR, NAND-NAND)
- Know XOR/XNOR are 1-bit comparators (XOR indicates "differ", XNOR indicates "same")

- Parity
- Understand why and how it is used
- Understand and be able to design parity generator/checker circuit

- Comparators
- Understand function
- Be able to design an
`n`-bit comparator

- Adders
- Understand function, truth table, etc. of a 1-bit Full Adder
- Know "S" and "Cout" equations (several forms)
- SOP form of equations, useful for PLA implementation
- XOR and NAND implementation
- Understand the trick used to combine logic between S/Cout outputs (change 'or' to 'xor' in the Cout equation)

- Know the symbol for a 1-bit full adder
- Be able to design a ripple carry adder from Full Adder building block

- Understand basic difference between combinational and sequential logic
- sequential: depends not only on current inputs, but past inputs too
- "state"
- clock, frequency/period
- picture of generalized FSM (Finite State Machine)

- Latches and Flip-Flops
- Derivation of storage element: "bistable element"
- S-R latch
- S-R latch with enable (enable introduces the "clock" signal)
- D latch
- derived from S-R latch
- "transparent mode" vs. "latched mode"

- Edge-triggered D Flip-Flop
- Built from Master & Slave D latches
- Understand derivation of "edge-triggered" behavior from master/slave latches

- T (toggle) Flip-Flop
- useful for frequency dividers and counters

- Miscellaneous
- Understand truth table, function, etc. of latches/flip-flops
- Understand logic inside latches/flip-flops
- Know and be able to use symbols for latches/flip-flops
- Positive-edge-triggered vs. negative-edge-triggered
- Asynchronous vs. synchronous inputs, e.g., asynchronous reset for initializing state

- State Machine Analysis
- General FSM
- state memory + clock
- next-state logic
- Next State = F(current state, inputs)

- output logic
- Moore machine: Output = G(current state)
- Mealy machine: Output = G(current state, inputs)

- Analyzing a sequential circuit
- Determine next-state equations and output equations
- Construct state table
- Draw state diagram (nodes and arcs)

- Understand state table formats, for Mealy and Moore
- Understand state diagram formats, for Mealy and Moore
- Be able to:
- go from state table to state diagram
- go from state diagram to state table
- generate a "state sequence chart" from a state table or state diagram, given an input sequence

- General FSM
- State Machine Synthesis
- Synthesizing a sequential circuit from a state table or state diagram
- Fill in K-maps
- Exploit unused states (dont-cares)
- Solve K-maps to get:
- Next-state equations: Q* = F(Q, inputs)
- Output equations
- Mealy: outputs = G(Q, inputs)
- Moore: outputs = G(Q)

- Draw the sequential circuit diagram (flip-flops and gates) based on the next-state and output equations

- Synthesizing a sequential circuit from a state table or state diagram
- State Machine Design
- Design a state machine from a description
- Know how to design sequence detectors

- Miscellaneous
- Know how to use the preset (PR) and clear (CLR) inputs of flip-flops to initialize a state machine
- State minimization (merging redundant states)
- State assignment, e.g., one-hot coding