Final review -- CSCI 311 / ENGR 212 / ECE 212

The final exam is comprehensive. You should also review the Quiz 1 and Quiz 2 review sheets.

The final is closed book. No calculators are allowed.

Chapter 8

• Counters (Section 8.4)
  • Modulo-m counter (m states)
  • Using MSI counters (e.g., 74x163) to build modulo-m counters
• Shift Registers (Section 8.5)
  • Serial vs. parallel loading, serial vs. parallel reading
  • Implementing sequence detectors using shift registers
• Datapath + Control: Synchronous Design Methodology (Section 8.7)
  • Understand and be able to draw the generic diagram of a synchronous system with datapath and control units
  • From problem description, be able to design datapath unit, control unit, and signals between the units and to/from the outside world
  • Given a diagram of a datapath, be able to analyze the datapath, figure out how register values change every cycle, and finally draw a conclusion about what function is performed by the system
  • Example datapaths: multiplier, divider
  • Datapath components
    • registers
    • MUXes
    • comparators
    • counters
    • adders, subtractors, ALUs
    • memories
  • Labeling signals/buses

Chapter 10

• Memory
  • Understand generic structure/diagram of a memory
  • Address decoder
  • Wordlines, bitlines, memory array
  • Sense amps and write circuitry
  • Naming of memories (2ⁿ x b memory)
  • Build larger memories out of smaller memories
  • Using MSI memory components
    • Address inputs
    • Data inputs/outputs
    • Chip Select (CS)
    • Write Enable (WE)
    • Output Enable (OE)
  • Memory traits
    • random access (RAM) vs. sequential
    • read-only (ROM) vs. read/write
    • volatile vs. non-volatile
    • different RAM technologies (e.g., SRAM, DRAM)
  • Memory types
    • PROM, EPROM, EEPROM, Flash
      • used for programmable logic
      • assist in booting a computer
      • store configuration information
      • used in consumer application
    • SRAM
      • know cell structure, reading, writing
      • fast but not dense (costly)
      • used in caches and register files
    • DRAM
      • know cell structure, reading, writing, refresh
      • slow but dense (cheap)
      • used in main memory
  • Caches and Memory Hierarchy
    • Understand why caches are used and why memory hierarchies exist (gives illusion of large memory system that is also fast)
    • Locality of Reference
      • Temporal Locality
      • Spatial Locality
    • Average access time equation with cache
    • Cache operation
      • memory blocks
      • computing # cache blocks in a cache, etc.
      • divide address into tag, index, block offset fields
      • cache structure, indexing method, tag match, etc.
      • be able to simulate a cache by applying an address stream
        • count number of accesses
        • count number of hits/misses
        • count number of replacements
        • calculate miss rate (# misses/# accesses)
        • given cache hit time & cache miss penalty, use miss rate to compute average access time
    • Cache implementation issues
      • Levels of caches (L1, L2, L3, ...)
      • Harvard architectures (D-cache, I-cache)
      • Cache conherency in multi-processors

Virtual memory

See the 27 April lecture notes.

• Virtual vs. logical addresses
• Basic page table structure
• Role of operating system in paging
• TLB -- Translation Lookaside Buffer