Draw the transistor-level structure for a single SRAM cell; do not show the transistors inside the inverters (instead, use the inverter symbol); be sure to label wordline and bitlines. Explain how the cell is read and written.
Draw the transistor-level structure for a single DRAM cell and explain how it is read and written. Make sure to label wordline and bitline. When and why does a DRAM cell have to be refreshed?
Draw a high-level block diagram of the internal organization of an 8K x 8 SRAM. Do not be concerned with details -- the idea is to show the dimensions of the SRAM and the widths of "buses".
Fill in the following table with "yes" or "no" in each box.
Flash and EEPROM | SRAM | DRAM | |
---|---|---|---|
non-volatile | YES | NO | NO |
periodic refresh required | NO | NO | YES |
destructive reads | NO | NO | YES |
relatively slow but very dense | leave blank | NO | YES |
relatively fast but not very dense | leave blank | YES | NO |
typically used for main memory | NO | NO | YES |
typically used for processor caches and register files | NO | YES | NO |
typically used to assist booting or to store configuration information | YES | NO | NO |
Show how to build a 512x8 ROM out of 64x16 ROM chips and appropriately sized decoders. Assume that the ROM chips you use in this problem have OE (output enable) and CS (chip select) inputs. Be sure to clearly label the address and data output connections of your solution.
Because (512x8)/(64x16) is 4, you'll need four 64x16 ROM chips to implment the 512x8 ROM. Since word size than the 64x16 ROM, you'll need a 8-bit wide 2-to-1 MUX to select 8 bits from the 16 produced by the 64x16 ROM. The 64x16 ROM's are placed in "rows" containing one 64x16 ROM. You'll need a 2-to-4 decoder do enable the correct row.
Since log2 512 is 9, the 512x8 ROM requires
nine address bits. The two most significant address bits are connected
to the 2-to-4 decoder. The least signifcant address bits is connected
to the single selector input of the 2-to-1 MUX.
This leaves six address bits to connect to the address lines of
the 64x16 ROM's. Since log2 64 is 6, all is well.
Implement the following functions using 16x1 ROMs:
f1 = Σ(0,1,2,6,7,9,11) and f2 = Σ(0,1,3,4,11,12,15): Show the labels for the inputs and outputs, and the content of ROM.
Just fill up two ROM according to the truth table.
A Mealy machine sequence detector that detects overlapping sequence '010': Show the state transition diagram, state assignment, state table, and the circuit that consists of D flip-flops and the memory (with its content).
There are many possible answers depending on your state assignment.
state | input | |
---|---|---|
0 | 0 | |
S | S0/0 | S/0 |
S0 | S0/0 | S01/0 |
S01 | S0/1 | S/0 |
state | |
---|---|
logical | binary |
S | 00 |
S0 | 1- |
S01 | 01 |
state | I | state | O | ||
---|---|---|---|---|---|
Q1 | Q0 | Q1* | Q0* | ||
0 | 0 | 0 | 1 | - | 0 |
0 | 0 | 1 | 0 | 0 | 0 |
0 | 1 | 0 | 1 | - | 1 |
0 | 1 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 1 | - | 0 |
1 | 0 | 1 | 0 | 1 | 0 |
1 | 1 | 0 | 1 | - | 0 |
1 | 1 | 1 | 0 | 1 | 0 |
This time you'll need three ROMs, two for the flip-flop inputs and one for the state machine output. Only eight rows of the ROM need to be filled.
For the following caches, determine the number of cache blocks. Also, partition and label a 32-bit address into the block offset field, index field, and tag field for the caches.
8KB direct mapped cache, with a block size of 64 bytes.
The number of block offset bits is log2 64 or 6. The number of cache blocks is 8k/64 or 128. Consequently, the number is of index bits is log2 128 or 7. The number of tag bits is 32-7-6 or 19.
16KB direct mapped cache, with a block size of 32 bytes.
The number of block offset bits is log2 32 or 5. The number of cache blocks is 16k/32 or 512. Consequently, the number is of index bits is log2 512 or 9. The number of tag bits is 32-9-5 or 18.
Apply the following address stream to a 256 byte direct mapped cache, with block size of 16 bytes.
The number of block offset bits is log2 16 or 4. The number of cache blocks is 256/16 or 16. Consequently, the number is of index bits is log2 16 or 4. The number of tag bits is 32-4-4 or 24.
The following table shows what happens when the addresses are applied in sequence:
address | tag | index | comments |
---|---|---|---|
0xfffec441 | 0xfffec4 | 0x4 | Miss |
0x07395a20 | 0x07395a | 0x2 | Miss |
0x00ee0224 | 0x00ee02 | 0x2 | Miss, replace 0x07395a |
0xbadbee44 | 0xbadbee | 0x4 | Miss, replace 0xfffec4 |
0x000099c0 | 0x000099 | 0xc | Miss |
0x000099c8 | 0x000099 | 0xc | Hit |
0xffffffc4 | 0xffffff | 0xc | Miss, replace 0x000099 |
0xbadbee4c | 0xbadbee | 0x4 | Hit |
Show the final contents of the cache. Only show the tags. Leave cache blocks that were not touched by the address stream blank.
block | tag |
---|---|
0 | |
1 | |
2 | 0x00ee02 |
3 | |
4 | 0xbadbee |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | 0xffffff |
13 | |
14 | |
15 |
How many cache hits were there? (Assume the cache is initially empty.)
2
How many replacements were there? (Assume the cache is initially empty.)
3