CSCI 311 / ENGR 212 / ECE 212 Homework Assignment 8

Problem 1

Problem 1(a)

Draw the transistor-level structure for a single SRAM cell; do not show the transistors inside the inverters (instead, use the inverter symbol); be sure to label wordline and bitlines. Explain how the cell is read and written.

Problem 1(b)

Draw the transistor-level structure for a single DRAM cell and explain how it is read and written. Make sure to label wordline and bitline. When and why does a DRAM cell have to be refreshed?

Problem 1(c)

Draw a high-level block diagram of the internal organization of an 8K x 8 SRAM. Do not be concerned with details -- the idea is to show the dimensions of the SRAM and the widths of "buses".

Show the memory storage array as a single box with width/height dimensions labeled.
Show the address decoder block, with the address bus coming in (label with the width of the bus) and wordlines coming out (no, don't draw all wordlines, just give the general idea).
Show the data bus (label with the width of the bus), i.e., bitlines, coming out of the memory structure.

Problem 1(d)

Fill in the following table with "yes" or "no" in each box.

	Flash and EEPROM	SRAM	DRAM
non-volatile
periodic refresh required
destructive reads
relatively slow but very dense	leave blank
relatively fast but not very dense	leave blank
typically used for main memory
typically used for processor caches and register files
typically used to assist booting or to store configuration information

Problem 2

Show how to build a 512x8 ROM out of 64x16 ROM chips and appropriately sized decoders. Assume that the ROM chips you use in this problem have OE (output enable) and CS (chip select) inputs. Be sure to clearly label the address and data output connections of your solution.

Problem 3

Implement the following functions using 16x1 ROMs:

f1 = Σ(0,1,2,6,7,9,11) and f2 = Σ(0,1,3,4,11,12,15): Show the labels for the inputs and outputs, and the content of ROM.
A Mealy machine sequence detector that detects overlapping sequence '010': Show the state transition diagram, state assignment, state table, and the circuit that consists of D flip-flops and the memory (with its content).

Problem 4

For the following caches, determine the number of cache blocks. Also, partition and label a 32-bit address into the block offset field, index field, and tag field for the caches.

8KB direct mapped cache, with a block size of 64 bytes.
16KB direct mapped cache, with a block size of 32 bytes.

Problem 5

Apply the following address stream to a 256 byte direct mapped cache, with block size of 16 bytes.

Show the final contents of the cache. Only show the tags. Leave cache blocks that were not touched by the address stream blank.
How many cache hits were there? (Assume the cache is initially empty.)
How many replacements were there? (Assume the cache is initially empty.)

0xfffec441
0x07395a20
0x00ee0224
0xbadbee44
0x000099c0
0x000099c8
0xffffffc4
0xbadbee4c