CSCI 311 / ENGR 212 / ECE 212 Homework Assignment 8

Problem 1

Problem 1(a)

Draw the transistor-level structure for a single SRAM cell; do not show the transistors inside the inverters (instead, use the inverter symbol); be sure to label wordline and bitlines. Explain how the cell is read and written.

Problem 1(b)

Draw the transistor-level structure for a single DRAM cell and explain how it is read and written. Make sure to label wordline and bitline. When and why does a DRAM cell have to be refreshed?

Problem 1(c)

Draw a high-level block diagram of the internal organization of an 8K x 8 SRAM. Do not be concerned with details -- the idea is to show the dimensions of the SRAM and the widths of "buses".

Problem 1(d)

Fill in the following table with "yes" or "no" in each box.

periodic refresh required   
destructive reads   
relatively slow but very denseleave blank  
relatively fast but not very denseleave blank  
typically used for main memory   
typically used for processor caches and register files   
typically used to assist booting or to store configuration information   

Problem 2

Show how to build a 512x8 ROM out of 64x16 ROM chips and appropriately sized decoders. Assume that the ROM chips you use in this problem have OE (output enable) and CS (chip select) inputs. Be sure to clearly label the address and data output connections of your solution.

Problem 3

Implement the following functions using 16x1 ROMs:

Problem 4

For the following caches, determine the number of cache blocks. Also, partition and label a 32-bit address into the block offset field, index field, and tag field for the caches.

Problem 5

Apply the following address stream to a 256 byte direct mapped cache, with block size of 16 bytes.