CSCI 311 / ENGR 212 / ECE 212 Homework Assignment 7

Problem 1

Write a VHDL behavioural specification for the majority function. Assume the input variables are X, Y, and Z and the output variable is M.

The answer should be a single line similar to:

Problem 2

Problem 2(a)

Design a 4-bit binary counter that counts modulo-9 with the counting sequence:

Design this as a custom circuit using gates and flip-flops. That is, begin with a state table and synthesize the circuit from the state table. Exploit don't-care states if applicable. Use an external asynchronous RESET input to initialize the flip-flops to the initial state.

Problem 2(b)

Repeat subproblem 2(a), but use a 74x163 as the basic building block, and add external logic to drive the counting sequence. Use an external synchronous input called init for initializing the counting sequence.

Problem 2(c)

Which approach was easier? Which approach was less expensive? Explain your answer.

Problem 3

Problem 3(a)

Design a Mealy state machine to detect the sequence 10010. There is a single input x and a single output z. The output is set to 1 when the sequence is detected

Design the state machine using gates and flip-flops in the standard way, i.e., begin with a state diagram and state table, do plain state assignment (e.g., for three state variables, first state is 000, next is 001, and so on), use K-maps to derive minimized next-state and output equations (exploit don't-care states if applicable), and synthesize the circuit diagram from the equations.

Problem 3(b)

Repeat problem 3(a), but this time use a shift register to design your circuit.

Problem 3(c)

Which approach was easier? Which approach was less expensive? Explain your answer.

Problem 4

Design a division circuit that will divide a 7-bit number by a 5-bit number. You'll do the division by successive subtraction, continually subtracting the 5-bit number from the 7-bit number until no further subtractions are possible. You'll then report the quotient and remainder of the operation.

Your design should include the datapath unit and the control unit of the system and the signals that interact between them. Your final design should show:

  1. A top-level diagram of the overall system showing
  2. A block diagram of the . Elements like ALUs, MUXs, comparators, registers, counters, etc., should be represented by an appropriate symbol and should not be shown at the level of individual gates.
  3. The state diagram for the control unit. You do not have to synthesize a circuit for your state machine.