This homework is due 13 May, 4:30 PM.
Design a 4-bit ripple counter using four D Flip-Flops and no other components. What limits the maximim counting speed of your counter?
Design a four-bit binary counter that counts through the following sequence of seven numbers: 7, 8, 9, 10, 11, 12, 13. Design this as a custom circuit using a state table and flip-flops of your choosing.
Now repeat your design of the counter, but use a 74x163 as the basic building block, and add external logic to drive the counting sequence.
In Homework 6, you were asked to design a state machine to detect the sequence 10110.
Repeat the problem from Homework 6, but use a shift register to design your circuit instead of state tables and associated circuits.
Design a circuit that will receive a 16-bit unsigned number, X, as input and produce as output an unsigned 4-bit number, Y, which is the remainder of dividing X by ten. You are to accomplish this task with an adder, a shifter, a counter, a MUX or two, and a couple of registers in your data unit.
This is not as hard as it appears. You start by loading Y into one register, which we'll call R. Into another register, which we'll call S, load the binary value 0110000000000000.
For thirteen steps do the following: Add R to S. If this results in a carry-out from the adder, then store R+S into R. If there is no carry-out, do not change the value of R. Then right-shift S on position and allows shirt a 1 into the left-most bit position of S.
Add the end of these thirteen steps, R holds the remainder of dividing X by ten.
Here are three examples where X is 56789, 8192, and 310, or, in binary, 1101110111010101, 0010000000000000, and 0000000100110110. Consequently, Y is 9, 2 and 0, or, in binary, 1001, 0010, and 0000.
| X | 1101110111010101 | 0010000000000000 | 0000000100110110 | |
| Step 1 | R | 1101110111010101 | 0010000000000000 | 0000000100110110 |
| S | 0110000000000000 | 0110000000000000 | 0011000000000000 | |
| R+S | 1+0011110111010101 | 0+1000000000000000 | 0+0011000100110110 | |
| Step 2 | R | 0011110111010101 | 0010000000000000 | 0000000100110110 |
| S | 1011000000000000 | 1011000000000000 | 1011000000000000 | |
| R+S | 0+1110110111010101 | 0+1101000000000000 | 0+1011000100110110 | |
| Step 3 | R | 0011110111010101 | 0010000000000000 | 0000000100110110 |
| S | 1101100000000000 | 1101100000000000 | 1101100000000000 | |
| R+S | 1+0001010111010101 | 0+1111100000000000 | 0+1101100100110110 | |
| Step 4 | R | 0001010111010101 | 0010000000000000 | 0000000100110110 |
| S | 1110110000000000 | 1110110000000000 | 1110110000000000 | |
| R+S | 1+0000000111010101 | 1+0000110000000000 | 0+1110110100110110 | |
| Step 5 | R | 0000000111010101 | 0000110000000000 | 0000000100110110 |
| S | 1111011000000000 | 1111011000000000 | 1111011000000000 | |
| R+S | 0+1111011111010101 | 1+0000001000000000 | 0+1111011100110110 | |
| Step 6 | R | 0000000111010101 | 0000001000000000 | 0000000100110110 |
| S | 1111101100000000 | 1111101100000000 | 1111101100000000 | |
| R+S | 0+1111110011010101 | 0+1111110100000000 | 0+1111110000110110 | |
| Step 7 | R | 0000000111010101 | 0000001000000000 | 0000000100110110 |
| S | 1111110110000000 | 1111110110000000 | 1111110110000000 | |
| R+S | 0+1111111101010101 | 0+1111111110000000 | 0+1111111010110110 | |
| Step 8 | R | 0000000111010101 | 0000001000000000 | 0000000100110110 |
| S | 1111111011000000 | 1111111011000000 | 1111111011000000 | |
| R+S | 1+0000000010010101 | 1+0000000011000000 | 0+1111111111110110 | |
| Step 9 | R | 0000000010010101 | 0000000011000000 | 0000000100110110 |
| S | 1111111101100000 | 1111111101100000 | 1111111101100000 | |
| R+S | 0+1111111111110101 | 1+0000000000100000 | 1+0000000010010110 | |
| Step 10 | R | 0000000010010101 | 0000000000100000 | 0000000010010110 |
| S | 1111111110110000 | 1111111110110000 | 1111111110110000 | |
| R+S | 1+0000000001000101 | 0+1111111111010000 | 1+0000000001000110 | |
| Step 11 | R | 0000000001000101 | 0000000000100000 | 0000000001000110 |
| S | 1111111111011000 | 1111111111011000 | 1111111111011000 | |
| R+S | 1+0000000000011101 | 0+1111111111111000 | 1+0000000000011110 | |
| Step 12 | R | 0000000000011101 | 0000000000100000 | 0000000000011110 |
| S | 1111111111101100 | 1111111111101100 | 1111111111101100 | |
| R+S | 1+0000000000001001 | 1+0000000000001100 | 1+0000000000001010 | |
| Step 13 | R | 0000000000001001 | 0000000000001100 | 0000000000001010 |
| S | 1111111111110110 | 1111111111110110 | 1111111111110110 | |
| R+S | 0+1111111111111111 | 1+0000000000000010 | 1+0000000000000000 | |
| Y | 0000000000001001 | 0000000000000010 | 0000000000000000 | |
In addition to the 16-bit input X, there is an input control signal XV which is set when X is valid. XV is cleared after one clock period. This signal should be used to initiate the division process. You may assume that XV is never asserted while another division is underway, only when the machine is idle.
In addition to the 4-bit output Y, there is an output control signal YV which is set when Y is valid. YV is also cleared after one clock period.
There is also a clock input CLK, used for clocking all flip-flops and registers.
Your design should include the data portion and the control portion of the system and the signals that interact between them. You'll have to design the state machine to control the data portion. The data portion will have to detect situations that require action in the control portion of the circuit.
Your design should show a schematic block diagram, all internal registers and control signals, the state diagram for the control section and the logic design for the control section.