This homework is due 19 March, 4:30 PM.

In this problem you are going to implement a PLA that
receives four bits, `a`_{1}, `a`_{0},
`b`_{1}, and `b`_{0}, as input
and produces the four bit result of multiplying
`a`_{1}`a`_{0}
by `b`_{1}`b`_{0}.
For example, if the four input bits are 1011, that's 10 and 11, and four output
bits should be 0110.

Write the boolean expressions you will use to implement this
function.
You will probably need to use `espresso` to get your
implementation to fit into the PLA.

Program the PLA show below by marking connections with an "X" to
contstruct the two-bit multiplier.
Label used inputs and outputs with the appropriate signal names.

Program the PLA below to construct a 3-to-8 Decoder. Include one active-low enable signal and one active-high enable signal.

Design a 2-bit 4:1 MUX using discrete logic gates. The 2-bit data inputs
are `A`, `B`, `C`, and `D`.
The 2-bit data output is `Y`.
Individual bits of `A` are `A`_{0} and
`A`_{1}, etc.
Assume the select control signals must be decoded.

Show how to build a quadruple 4-line to 1-line multiplexers using three quadruple 2-line to 1-line data selectors, in particular the 74157. Use the datasheet for TI's SN74F157A in generating your implementation.

Design a 2-bit comparator for two-bit values `A` and `B`.
The comparator has a single output, but two control inputs
`C`_{1} and `C`_{0}.
The output is set using the control inputs as follows:

C_{1} |
C_{0} |
output |
---|---|---|

0 | 0 | 0 |

0 | 1 | A ≤ B |

1 | 0 | A ≥ B |

1 | 1 | A ≡ B |