library IEEE; use IEEE.std_logic_1164.all; library SYNOPSYS; use SYNOPSYS.attributes.all; entity smexamp is port ( CLOCK, A, B: in STD_LOGIC; Z: out STD_LOGIC ); end; architecture smexamp_arch of smexamp is type Sreg_type is (INIT, A0, A1, OK0, OK1); attribute enum_encoding of Sreg_type: type is "0000 0001 0010 0100 1000"; signal Sreg: Sreg_type; begin process (CLOCK) -- state-machine states and transitions begin if CLOCK'event and CLOCK = '1' then case Sreg is when INIT => if A='0' then Sreg <= A0; elsif A='1' then Sreg <= A1; end if; when A0 => if A='0' then Sreg <= OK0; elsif A='1' then Sreg <= A1; end if; when A1 => if A='0' then Sreg <= A0; elsif A='1' then Sreg <= OK1; end if; when OK0 => if A='0' then Sreg <= OK0; elsif A='1' and B='0' then Sreg <= A1; elsif A='1' and B='1' then Sreg <= OK1; end if; when OK1 => if A='0' and B='0' then Sreg <= A0; elsif A='0' and B='1' then Sreg <= OK0; elsif A='1' then Sreg <= OK1; end if; when others => Sreg <= INIT; end case; end if; end process; with Sreg select -- output values based on state Z <= '0' when INIT | A0 | A1, '1' when OK0 | OK1, '0' when others; end smexamp_arch;