# Spring 2002 ENGR 212 / CSCI 311 Homework 6

## Problem 1

### Subproblem 1A

Here is the espresso input for the problem.

```# Espresso for problem 1a
.i 5
.o 3
.ilb a b c d e
.ob F G H
.p 32
00000 1-0
00001 0-0
00010 --0
00011 0-0
00100 --0
00101 1-0
00110 0-0
00111 ---
01000 000
01001 000
01010 000
01011 000
01100 001
01101 011
01110 001
01111 011
10000 000
10001 100
10010 000
10011 100
10100 001
10101 101
10110 001
10111 001
11000 000
11001 110
11010 000
11011 000
11100 000
11101 000
11110 00-
11111 101
.e
```

Here is the espresso output for the problem.

```# Espresso for problem 1a
.i 5
.o 3
.ilb a b c d e
.ob F G H
.p 8
00-00 100
11001 110
11111 101
100-1 100
-0101 100
011-- 001
0-1-1 010
101-- 001
.e
```

Consequently, the three functions can be implemented as:

• F(a, b, c, d, e) = a' b' d' e' + a b c' d' e + a b c d e + a b' c' e + b' c d' e
• G(a, b, c, d, e) = a b c' d' e + a' c e
• H(a, b, c, d, e) = a b c d e + a' b c + a b' c

And finally, here is the PLA

### Subproblem 1B

Again, here is espresso input

```# Problem 1B
.i 4
.o 2
.ilb a0 a1 b0 b1
.ob GT LT
.p 16
0000 00
0001 01
0010 01
0011 01
0100 10
0101 00
0110 00
0111 01
1000 10
1001 00
1010 00
1011 01
1100 10
1101 10
1110 10
1111 00
.e
```

And here is espresso output

```# Problem 1B
.i 4
.o 2
.ilb a0 a1 b0 b1
.ob GT LT
.p 8
1-00 10
-100 10
11-0 10
110- 10
001- 01
00-1 01
-011 01
0-11 01
.e
```

Consequently, the three functions can be implemented as:

• GT(a0, a1, b0, b1) = a0 b0' b1' + a1 b0' b1' + a0 a1 b0' + a0 a1 b1'
• LT(a0, a1, b0, b1) = a1' a0' b0 + a1' a0' b1 + a1' b0 b1 + a0' b0 b1

And finally, here is the PLA

## Problem 2

Write "programs" to solve Subproblem 1B in both ABEL and VHDL. Be sure to test out your programs using Xilinx Foundation.

```module HW6P2
title 'Howmework 6 Problem 2'

A0, A1, B0, B1 PIN ;
GT, LT PIN istype 'com' ;

A0num = [0, A0] ;
A1num = [0, A1] ;
B0num = [0, B0] ;
B1num = [0, B1] ;

equations
GT = (A0num+A1num) > (B0num+B1num) ;
LT = (A0num+A1num) < (B0num+B1num) ;

end HW6P2
```
```library ieee ;
use ieee.std_logic_1164.all ;

entity HW6P2 is

port (
A  : in STD_LOGIC_VECTOR (0 to 1);
B  : in STD_LOGIC_VECTOR (0 to 1);
GT : out STD_LOGIC;
LT : out STD_LOGIC
) ;

end HW6P2 ;

architecture HW6P2_arch_jdb of HW6P2 is

function POPULATION (X: STD_LOGIC_VECTOR) return INTEGER is
variable RESULT : INTEGER ;
begin
RESULT := 0 ;
for i in X'range loop
case X(i) is
when '1' | 'H' => RESULT := RESULT + 1;
when others => null;
end case;
end loop;  -- i
return RESULT;
end POPULATION ;

begin  -- HW6P2_arch_jdb

GT <= '1' when POPULATION(A) > POPULATION(B)
else '0' ;
LT <= '1' when POPULATION(A) < POPULATION(B)
else '0' ;

end HW6P2_arch_jdb;
```