24 April, 2000

Seven concepts (in 2000) of high speed processor design

Proccess block diagram
The PC Technology Guide is a good on-line source of information about the architecture of the Intel processors.

processor vs. memory
- on chip access -- 1 nanosecond
- off chip access -- 100 nanoseconds
cache hierachy
- L1
  - typically on-chip
  - small -- 32 kbytes
  - often divided into I and D caches
- L2
  - typically SRAM
  - larger -- 1 Mbyte
  - COASt -- Cache On A Stick
Locality
- temporal
- spatial
Properties
- cache size
- block size
  - related to memory access
  - exploits spatial locality
Implementation details
- Writing changes to DRAM
  - write through
  - write back
- Tagging the memory
Paging -- DRAM as a cache

Cyrix pipeline

Alpha Integer Instruction Pipeline Stages
IF	Instruction fetch
SWAP	Swap dual issue instruction	Branch prediction
I0	Decode
I1	Register file(s) access	Issue check
A1	Computation cycle 1	Ibox computes new PC
A2	Computation cycle 2	Instruction translation buffer (TB) lookup
WR	Integer register file write	Instruction cache hit/Miss