27 March, 2000

New due dates

• Homework
• Problem sets

Registers

• Extension of the D flip-flop
• Clocked load
• Asynchronous clear and preset

Shift registers

• serial-in/parallel-out
  • One data input
  • m data outputs
• parallel load
  • One data input
  • m data inputs
  • m data outputs
  • possibly one left data input
  • possibly one right data input
  • load control input

counters

• binary counters
  • m data outputs
  • one enable control input
  • one asynchronous clear input
• BCD counters
  • "turn over" in base 10
• asynchronous counters
  • look maw, no clocks

Animation

• a little diglog